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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-09 14:09:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-09 14:09:22 +0200 |
| commit | f7435eca9639b1a5639867364d88c4fd957a034d (patch) | |
| tree | 1e801e3b468ff22475083a071f831d268ab7f13c /scripts | |
| parent | 649faca27ef0229f7844a4680290693674d775b3 (diff) | |
| download | picorv32-f7435eca9639b1a5639867364d88c4fd957a034d.tar.gz picorv32-f7435eca9639b1a5639867364d88c4fd957a034d.zip | |
Improvements in scripts/torture/
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/torture/Makefile | 4 | ||||
| -rw-r--r-- | scripts/torture/riscv-isa-sim-notrap.diff | 16 | ||||
| -rw-r--r-- | scripts/torture/testbench.v | 4 |
3 files changed, 23 insertions, 1 deletions
diff --git a/scripts/torture/Makefile b/scripts/torture/Makefile index 90dbc24..8856a7a 100644 --- a/scripts/torture/Makefile +++ b/scripts/torture/Makefile @@ -18,7 +18,9 @@ riscv-fesvr/build.ok: riscv-isa-sim/build.ok: riscv-fesvr/build.ok rm -rf riscv-isa-sim git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim - cd riscv-isa-sim && git checkout 10ae74e && patch -p1 < ../riscv-isa-sim-sbreak.diff + cd riscv-isa-sim && git checkout 10ae74e + cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-sbreak.diff + cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-notrap.diff cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC +cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok diff --git a/scripts/torture/riscv-isa-sim-notrap.diff b/scripts/torture/riscv-isa-sim-notrap.diff new file mode 100644 index 0000000..df7c059 --- /dev/null +++ b/scripts/torture/riscv-isa-sim-notrap.diff @@ -0,0 +1,16 @@ +diff --git a/riscv/processor.cc b/riscv/processor.cc +index 3b834c5..e112029 100644 +--- a/riscv/processor.cc ++++ b/riscv/processor.cc +@@ -201,9 +201,10 @@ void processor_t::set_privilege(reg_t prv) + + void processor_t::take_trap(trap_t& t, reg_t epc) + { +- if (debug) ++ // if (debug) + fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n", + id, t.name(), epc); ++ exit(1); + + // by default, trap to M-mode, unless delegated to S-mode + reg_t bit = t.cause(); diff --git a/scripts/torture/testbench.v b/scripts/torture/testbench.v index d55d9c1..d6b974f 100644 --- a/scripts/torture/testbench.v +++ b/scripts/torture/testbench.v @@ -48,6 +48,10 @@ module testbench ( repeat (10) @(posedge clk); resetn <= 1; + + repeat (100000) @(posedge clk); + $display("FAILED: Timeout!"); + $finish; end always @(posedge clk) begin |