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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-26 10:03:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-26 10:03:37 +0200 |
| commit | 9a4a06d981d1b2787b3f42907c3cd21b95cdfaf0 (patch) | |
| tree | 70b9b773cec4a59578e6a370a3383cc89b0cb302 /testbench.v | |
| parent | 9d26ebcf58a7326167d175d9458e04950371b9cb (diff) | |
| download | picorv32-9a4a06d981d1b2787b3f42907c3cd21b95cdfaf0.tar.gz picorv32-9a4a06d981d1b2787b3f42907c3cd21b95cdfaf0.zip | |
Refactoring of IRQ handling
Diffstat (limited to 'testbench.v')
| -rw-r--r-- | testbench.v | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/testbench.v b/testbench.v index b9914f5..5bfff25 100644 --- a/testbench.v +++ b/testbench.v @@ -6,9 +6,15 @@ module testbench; reg clk = 1; reg resetn = 0; - wire irq = &uut.picorv32_core.count_cycle[12:0]; + reg [31:0] irq; wire trap; + always @* begin + irq = 0; + irq[4] = &uut.picorv32_core.count_cycle[12:0]; + irq[5] = &uut.picorv32_core.count_cycle[15:0]; + end + always #5 clk = ~clk; initial begin @@ -39,13 +45,10 @@ module testbench; reg [31:0] mem_axi_rdata; picorv32_axi #( - .ENABLE_EXTERNAL_IRQ (1), - .ENABLE_ILLINSTR_IRQ (1), - .ENABLE_TIMER_IRQ (1) + .ENABLE_IRQ(1) ) uut ( .clk (clk ), .resetn (resetn ), - .irq (irq ), .trap (trap ), .mem_axi_awvalid(mem_axi_awvalid), .mem_axi_awready(mem_axi_awready), @@ -63,7 +66,8 @@ module testbench; .mem_axi_arprot (mem_axi_arprot ), .mem_axi_rvalid (mem_axi_rvalid ), .mem_axi_rready (mem_axi_rready ), - .mem_axi_rdata (mem_axi_rdata ) + .mem_axi_rdata (mem_axi_rdata ), + .irq (irq ) ); reg [31:0] memory [0:64*1024/4-1]; |