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author | Clifford Wolf <clifford@clifford.at> | 2016-04-10 16:54:35 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-04-10 16:54:35 +0200 |
commit | 00dd6ac38ee7e0b948a0a30d36f2e7a6fc2369ea (patch) | |
tree | 3e9c9c7b9fb8215da0a309cab8845e7bbb87d305 /tests | |
parent | 8f5845310950ee00dbc3084e76e3f11dd8493158 (diff) | |
download | picorv32-00dd6ac38ee7e0b948a0a30d36f2e7a6fc2369ea.tar.gz picorv32-00dd6ac38ee7e0b948a0a30d36f2e7a6fc2369ea.zip |
Added ENABLE_DIV and picorv32_pcpi_div
Diffstat (limited to 'tests')
-rw-r--r-- | tests/div.S | 41 | ||||
-rw-r--r-- | tests/divu.S | 41 | ||||
-rw-r--r-- | tests/rem.S | 41 | ||||
-rw-r--r-- | tests/remu.S | 41 |
4 files changed, 164 insertions, 0 deletions
diff --git a/tests/div.S b/tests/div.S new file mode 100644 index 0000000..a4504a7 --- /dev/null +++ b/tests/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/divu.S b/tests/divu.S new file mode 100644 index 0000000..cd348c9 --- /dev/null +++ b/tests/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 715827879, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/rem.S b/tests/rem.S new file mode 100644 index 0000000..c318e2c --- /dev/null +++ b/tests/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/remu.S b/tests/remu.S new file mode 100644 index 0000000..38d641d --- /dev/null +++ b/tests/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |