diff options
| -rw-r--r-- | README.md | 26 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_large.tcl | 3 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_regular.tcl | 3 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_small.tcl | 3 | ||||
| -rw-r--r-- | scripts/vivado/tabtest.sh | 3 | ||||
| -rw-r--r-- | scripts/vivado/tabtest.v | 2 |
6 files changed, 22 insertions, 18 deletions
@@ -545,7 +545,7 @@ The following evaluations have been performed with Vivado 2015.1. #### Timing on Xilinx 7-Series FPGAs -The `picorv32_axi` module with enabled `TWO_CYCLE_COMPARE` has been placed and +The `picorv32_axi` module with enabled `TWO_CYCLE_ALU` has been placed and routed for Xilinx Artix-7T (xc7a15t-fgg484), Xilinx Kintex-7T (xc7k70t-fbg676), and Xilinx Virtex-7T (xc7v585t-ffg1761) devices in all speed grades. A binary search is used to find the lowest clock period for which the design meets @@ -555,15 +555,15 @@ See `make table.txt` in [scripts/vivado/](scripts/vivado/). | Device | Speedgrade | Clock Period (Freq.) | |:-------------------- |:----------:| --------------------:| -| Xilinx Artix-7T | -1 | 4.6 ns (217 MHz) | -| Xilinx Artix-7T | -2 | 4.0 ns (250 MHz) | -| Xilinx Artix-7T | -3 | 3.4 ns (294 MHz) | -| Xilinx Kintex-7T | -1 | 3.0 ns (333 MHz) | -| Xilinx Kintex-7T | -2 | 2.7 ns (370 MHz) | -| Xilinx Kintex-7T | -3 | 2.5 ns (400 MHz) | -| Xilinx Virtex-7T | -1 | 3.0 ns (333 MHz) | -| Xilinx Virtex-7T | -2 | 2.5 ns (400 MHz) | -| Xilinx Virtex-7T | -3 | 2.2 ns (454 MHz) | +| Xilinx Artix-7T | -1 | 4.3 ns (232 MHz) | +| Xilinx Artix-7T | -2 | 3.4 ns (294 MHz) | +| Xilinx Artix-7T | -3 | 3.0 ns (333 MHz) | +| Xilinx Kintex-7T | -1 | 2.8 ns (357 MHz) | +| Xilinx Kintex-7T | -2 | 2.2 ns (454 MHz) | +| Xilinx Kintex-7T | -3 | 2.1 ns (476 MHz) | +| Xilinx Virtex-7T | -1 | 2.8 ns (357 MHz) | +| Xilinx Virtex-7T | -2 | 2.2 ns (454 MHz) | +| Xilinx Virtex-7T | -3 | 2.1 ns (476 MHz) | #### Utilization on Xilinx 7-Series FPGAs @@ -583,7 +583,7 @@ See `make area` in [scripts/vivado/](scripts/vivado/). | Core Variant | Slice LUTs | LUTs as Memory | Slice Registers | |:------------------ | ----------:| --------------:| ---------------:| -| PicoRV32 (small) | 775 | 48 | 422 | -| PicoRV32 (regular) | 960 | 48 | 564 | -| PicoRV32 (large) | 1684 | 88 | 1002 | +| PicoRV32 (small) | 770 | 48 | 422 | +| PicoRV32 (regular) | 938 | 48 | 564 | +| PicoRV32 (large) | 1710 | 88 | 1002 | diff --git a/scripts/vivado/synth_area_large.tcl b/scripts/vivado/synth_area_large.tcl index 55b0248..af611b5 100644 --- a/scripts/vivado/synth_area_large.tcl +++ b/scripts/vivado/synth_area_large.tcl @@ -3,7 +3,8 @@ read_verilog synth_area_top.v read_xdc synth_area.xdc synth_design -part xc7k70t-fbg676 -top top_large -opt_design -resynth_seq_area +opt_design -sweep -propconst -resynth_seq_area +opt_design -directive ExploreSequentialArea report_utilization report_timing diff --git a/scripts/vivado/synth_area_regular.tcl b/scripts/vivado/synth_area_regular.tcl index d7a8e34..2bf6b4c 100644 --- a/scripts/vivado/synth_area_regular.tcl +++ b/scripts/vivado/synth_area_regular.tcl @@ -3,7 +3,8 @@ read_verilog synth_area_top.v read_xdc synth_area.xdc synth_design -part xc7k70t-fbg676 -top top_regular -opt_design -resynth_seq_area +opt_design -sweep -propconst -resynth_seq_area +opt_design -directive ExploreSequentialArea report_utilization report_timing diff --git a/scripts/vivado/synth_area_small.tcl b/scripts/vivado/synth_area_small.tcl index c9a8a22..11d2104 100644 --- a/scripts/vivado/synth_area_small.tcl +++ b/scripts/vivado/synth_area_small.tcl @@ -3,7 +3,8 @@ read_verilog synth_area_top.v read_xdc synth_area.xdc synth_design -part xc7k70t-fbg676 -top top_small -opt_design -resynth_seq_area +opt_design -sweep -propconst -resynth_seq_area +opt_design -directive ExploreSequentialArea report_utilization report_timing diff --git a/scripts/vivado/tabtest.sh b/scripts/vivado/tabtest.sh index b481014..4ebd925 100644 --- a/scripts/vivado/tabtest.sh +++ b/scripts/vivado/tabtest.sh @@ -28,7 +28,8 @@ synth_case() { read_verilog ../../../picorv32.v read_xdc test_${1}.xdc synth_design -flatten_hierarchy full -part ${xl_device} -top top - opt_design -sweep -remap + opt_design -sweep -remap -propconst + opt_design -directive Explore place_design -directive Explore phys_opt_design -retime -rewire -critical_pin_opt -placement_opt -critical_cell_opt route_design -directive Explore diff --git a/scripts/vivado/tabtest.v b/scripts/vivado/tabtest.v index de75b11..cdf2057 100644 --- a/scripts/vivado/tabtest.v +++ b/scripts/vivado/tabtest.v @@ -73,7 +73,7 @@ module top ( delay4 #(32) delay_eoi (clk, eoi , io_eoi ); picorv32_axi #( - .TWO_CYCLE_COMPARE(1) + .TWO_CYCLE_ALU(1) ) cpu ( .clk (clk ), .resetn (resetn ), |