diff options
| -rw-r--r-- | README.md | 4 | ||||
| -rw-r--r-- | tests/srli.S | 4 | ||||
| -rw-r--r-- | tests/test_macros.h | 127 |
3 files changed, 6 insertions, 129 deletions
@@ -531,7 +531,7 @@ pure RV32I target, and install it in `/opt/riscv32i`: git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i cd riscv-gnu-toolchain-rv32i - git checkout 1d8d8bc + git checkout 4bcd4f5 mkdir build; cd build ../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i @@ -541,7 +541,7 @@ The commands will all be named using the prefix `riscv32-unknown-elf-`, which makes it easy to install them side-by-side with the regular riscv-tools, which are using the name prefix `riscv64-unknown-elf-` by default. -*Note: This instructions are for git rev 1d8d8bc (2015-11-21) of riscv-gnu-toolchain.* +*Note: This instructions are for git rev 4bcd4f5 (2015-12-14) of riscv-gnu-toolchain.* Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs diff --git a/tests/srli.S b/tests/srli.S index be56dc3..c2797cd 100644 --- a/tests/srli.S +++ b/tests/srli.S @@ -48,11 +48,11 @@ RVTEST_CODE_BEGIN TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - + TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 ); TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 ); TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 ); - + TEST_IMM_ZEROSRC1( 28, srli, 0, 31 ); TEST_IMM_ZERODEST( 29, srli, 33, 20 ); diff --git a/tests/test_macros.h b/tests/test_macros.h index 6242f0b..05ed7c8 100644 --- a/tests/test_macros.h +++ b/tests/test_macros.h @@ -286,7 +286,7 @@ test_ ## testnum: \ test_ ## testnum: \ li TESTNUM, testnum; \ li x4, 0; \ -1: la x1, result; \ +1: li x1, result; \ TEST_INSERT_NOPS_ ## src1_nops \ la x2, base; \ TEST_INSERT_NOPS_ ## src2_nops \ @@ -304,7 +304,7 @@ test_ ## testnum: \ li x4, 0; \ 1: la x2, base; \ TEST_INSERT_NOPS_ ## src1_nops \ - la x1, result; \ + li x1, result; \ TEST_INSERT_NOPS_ ## src2_nops \ store_inst x1, offset(x2); \ load_inst x3, offset(x2); \ @@ -564,129 +564,6 @@ test_ ## testnum: \ .double result; \ 1: - -#----------------------------------------------------------------------- -# RV64SV MACROS -#----------------------------------------------------------------------- - -#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \ - la a0, handler ## testnum; \ - csrw stvec, a0; \ - vsetcfg nxreg, nfreg; \ - li a0, 4; \ - vsetvl a0, a0; \ - la a0, src1; \ - la a1, src2; \ - vld vx2, a0; \ - vld vx3, a1; \ - lui a0,%hi(vtcode1 ## testnum); \ - vf %lo(vtcode1 ## testnum)(a0); \ - la reg2, dest; \ -illegal ## testnum: \ - inst reg1, reg2; \ - la a3, dest; \ - vsd vx2, a3; \ - fence; \ -vtcode1 ## testnum: \ - add x2, x2, x3; \ - stop; \ -vtcode2 ## testnum: \ - add x2, x2, x3; \ - stop; \ -handler ## testnum: \ - vxcptkill; \ - li TESTNUM,2; \ - csrr a0, scause; \ - li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \ - bne a0,a1,fail; \ - csrr a0, sbadaddr; \ - la a1, illegal ## testnum; \ - lw a2, 0(a1); \ - bne a0, a2, fail; \ - vsetcfg 32,0; \ - li a0,4; \ - vsetvl a0,a0; \ - la a0,src1; \ - la a1,src2; \ - vld vx2,a0; \ - vld vx3,a1; \ - lui a0,%hi(vtcode2 ## testnum); \ - vf %lo(vtcode2 ## testnum)(a0); \ - la a3,dest; \ - vsd vx2,a3; \ - fence; \ - ld a1,0(a3); \ - li a2,5; \ - li TESTNUM,2; \ - bne a1,a2,fail; \ - ld a1,8(a3); \ - li TESTNUM,3; \ - bne a1,a2,fail; \ - ld a1,16(a3); \ - li TESTNUM,4; \ - bne a1,a2,fail; \ - ld a1,24(a3); \ - li TESTNUM,5; \ - bne a1,a2,fail; \ - -#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ - la a0, handler ## testnum; \ - csrw stvec, a0; \ - vsetcfg nxreg, nfreg; \ - li a0, 4; \ - vsetvl a0, a0; \ - la a0, src1; \ - la a1, src2; \ - vld vx2, a0; \ - vld vx3, a1; \ - lui a0,%hi(vtcode1 ## testnum); \ - vf %lo(vtcode1 ## testnum)(a0); \ - la a3, dest; \ - vsd vx2, a3; \ - fence; \ -vtcode1 ## testnum: \ - add x2, x2, x3; \ -illegal ## testnum: \ - inst reg1, reg2, reg3; \ - stop; \ -vtcode2 ## testnum: \ - add x2, x2, x3; \ - stop; \ -handler ## testnum: \ - vxcptkill; \ - li TESTNUM,2; \ - csrr a0, scause; \ - li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \ - bne a0,a1,fail; \ - csrr a0, sbadaddr; \ - la a1,illegal ## testnum; \ - bne a0,a1,fail; \ - vsetcfg 32,0; \ - li a0,4; \ - vsetvl a0,a0; \ - la a0,src1; \ - la a1,src2; \ - vld vx2,a0; \ - vld vx3,a1; \ - lui a0,%hi(vtcode2 ## testnum); \ - vf %lo(vtcode2 ## testnum)(a0); \ - la a3,dest; \ - vsd vx2,a3; \ - fence; \ - ld a1,0(a3); \ - li a2,5; \ - li TESTNUM,2; \ - bne a1,a2,fail; \ - ld a1,8(a3); \ - li TESTNUM,3; \ - bne a1,a2,fail; \ - ld a1,16(a3); \ - li TESTNUM,4; \ - bne a1,a2,fail; \ - ld a1,24(a3); \ - li TESTNUM,5; \ - bne a1,a2,fail; \ - #----------------------------------------------------------------------- # Pass and fail code (assumes test num is in TESTNUM) #----------------------------------------------------------------------- |