diff options
| -rw-r--r-- | README.md | 12 | ||||
| -rw-r--r-- | scripts/vivado/Makefile | 5 | ||||
| -rw-r--r-- | scripts/vivado/synth_area.tcl | 5 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_large.tcl | 5 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_regular.tcl | 4 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_small.tcl | 4 |
6 files changed, 15 insertions, 20 deletions
@@ -533,7 +533,7 @@ place&route static timing analysis with `report_timing`. | Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) | The following table lists the resource utilization in area-optimized synthesis, -as reported by Vivado 2015.1 post optimization with `report_utilization`. +as reported by Vivado 2015.2 post optimization with `report_utilization`. PicoRV32 "small" is the core without counter instructions, with externally latched `mem_rdata`, and without catching of misaligned memory access and @@ -543,9 +543,9 @@ PicoRV32 "regular" is simply the core with its default settings. And PicoRV32 "large" is with enabled PCPI, IRQ and MUL features. -| Core Variant | Slice LUTs | LUTs as Memory | -|:------------------ | ----------:| --------------:| -| PicoRV32 "small" | 828 | 48 | -| PicoRV32 "regular" | 968 | 48 | -| PicoRV32 "large" | 1742 | 88 | +| Core Variant | Slice LUTs | LUTs as Memory | Slice Registers | +|:------------------ | ----------:| --------------:| ---------------:| +| PicoRV32 "small" | 828 | 48 | 422 | +| PicoRV32 "regular" | 968 | 48 | 564 | +| PicoRV32 "large" | 1742 | 88 | 1002 | diff --git a/scripts/vivado/Makefile b/scripts/vivado/Makefile index 01d36b1..17b9700 100644 --- a/scripts/vivado/Makefile +++ b/scripts/vivado/Makefile @@ -1,5 +1,5 @@ -export VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado +export VIVADO = /opt/Xilinx/Vivado/2015.2/bin/vivado help: @echo "Usage: make {synth_speed|synth_area|synth_soc}" @@ -14,6 +14,9 @@ synth_%: tab_%/results.txt: bash tabtest.sh $@ +area: synth_area_small synth_area_regular synth_area_large + -grep -B4 -A10 'Slice LUTs' synth_area_small.log synth_area_regular.log synth_area_large.log + table.txt: tab_small_xc7a_1/results.txt tab_small_xc7a_2/results.txt tab_small_xc7a_3/results.txt table.txt: tab_small_xc7k_1/results.txt tab_small_xc7k_2/results.txt tab_small_xc7k_3/results.txt table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_xc7v_3/results.txt diff --git a/scripts/vivado/synth_area.tcl b/scripts/vivado/synth_area.tcl index 804fd9a..b2c11e9 100644 --- a/scripts/vivado/synth_area.tcl +++ b/scripts/vivado/synth_area.tcl @@ -1,11 +1,8 @@ - read_verilog ../../picorv32.v -read_verilog synth_area_top.v read_xdc synth_area.xdc -synth_design -part xc7k70t-fbg676 -top top_large +synth_design -part xc7k70t-fbg676 -top picorv32_axi opt_design -resynth_seq_area report_utilization # report_timing - diff --git a/scripts/vivado/synth_area_large.tcl b/scripts/vivado/synth_area_large.tcl index 9c3633e..32d90f8 100644 --- a/scripts/vivado/synth_area_large.tcl +++ b/scripts/vivado/synth_area_large.tcl @@ -1,10 +1,9 @@ - read_verilog ../../picorv32.v +read_verilog synth_area_top.v read_xdc synth_area.xdc -synth_design -part xc7k70t-fbg676 -top picorv32_axi +synth_design -part xc7k70t-fbg676 -top top_large opt_design -resynth_seq_area report_utilization # report_timing - diff --git a/scripts/vivado/synth_area_regular.tcl b/scripts/vivado/synth_area_regular.tcl index 06b064c..a352ac4 100644 --- a/scripts/vivado/synth_area_regular.tcl +++ b/scripts/vivado/synth_area_regular.tcl @@ -1,11 +1,9 @@ - read_verilog ../../picorv32.v read_verilog synth_area_top.v read_xdc synth_area.xdc -synth_design -part xc7k70t-fbg676 -top top_small +synth_design -part xc7k70t-fbg676 -top top_regular opt_design -resynth_seq_area report_utilization # report_timing - diff --git a/scripts/vivado/synth_area_small.tcl b/scripts/vivado/synth_area_small.tcl index f8506b3..4a809b6 100644 --- a/scripts/vivado/synth_area_small.tcl +++ b/scripts/vivado/synth_area_small.tcl @@ -1,11 +1,9 @@ - read_verilog ../../picorv32.v read_verilog synth_area_top.v read_xdc synth_area.xdc -synth_design -part xc7k70t-fbg676 -top top_regular +synth_design -part xc7k70t-fbg676 -top top_small opt_design -resynth_seq_area report_utilization # report_timing - |