diff options
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | picorv32_wrapper.v | 118 | ||||
| -rw-r--r-- | testbench.v | 106 |
3 files changed, 129 insertions, 103 deletions
@@ -33,12 +33,12 @@ test_axi: testbench.exe firmware/firmware.hex test_synth: testbench_synth.exe firmware/firmware.hex vvp -N testbench_synth.exe -testbench.exe: testbench.v axi4_memory.v picorv32.v - iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v axi4_memory.v picorv32.v +testbench.exe: testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v + iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v chmod -x testbench.exe -testbench_sp.exe: testbench.v axi4_memory.v picorv32.v - iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v axi4_memory.v picorv32.v +testbench_sp.exe: testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v + iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v chmod -x testbench_sp.exe testbench_synth.exe: testbench.v synth.v diff --git a/picorv32_wrapper.v b/picorv32_wrapper.v new file mode 100644 index 0000000..ee16a14 --- /dev/null +++ b/picorv32_wrapper.v @@ -0,0 +1,118 @@ +// This is free and unencumbered software released into the public domain. +// +// Anyone is free to copy, modify, publish, use, compile, sell, or +// distribute this software, either in source code form or as a compiled +// binary, for any purpose, commercial or non-commercial, and by any +// means. + +module picorv32_wrapper #( + parameter AXI_TEST = 0, + parameter VERBOSE = 0 +) ( + input clk, + input resetn +); + + wire trap; + reg [31:0] irq; + + always @* begin + irq = 0; + irq[4] = &uut.picorv32_core.count_cycle[12:0]; + irq[5] = &uut.picorv32_core.count_cycle[15:0]; + end + + wire mem_axi_awvalid; + wire mem_axi_awready; + wire [31:0] mem_axi_awaddr; + wire [ 2:0] mem_axi_awprot; + + wire mem_axi_wvalid; + wire mem_axi_wready; + wire [31:0] mem_axi_wdata; + wire [ 3:0] mem_axi_wstrb; + + wire mem_axi_bvalid; + wire mem_axi_bready; + + wire mem_axi_arvalid; + wire mem_axi_arready; + wire [31:0] mem_axi_araddr; + wire [ 2:0] mem_axi_arprot; + + wire mem_axi_rvalid; + wire mem_axi_rready; + wire [31:0] mem_axi_rdata; + + axi4_memory #( + .AXI_TEST (AXI_TEST), + .VERBOSE (VERBOSE) + ) mem ( + .clk (clk ), + .mem_axi_awvalid (mem_axi_awvalid ), + .mem_axi_awready (mem_axi_awready ), + .mem_axi_awaddr (mem_axi_awaddr ), + .mem_axi_awprot (mem_axi_awprot ), + + .mem_axi_wvalid (mem_axi_wvalid ), + .mem_axi_wready (mem_axi_wready ), + .mem_axi_wdata (mem_axi_wdata ), + .mem_axi_wstrb (mem_axi_wstrb ), + + .mem_axi_bvalid (mem_axi_bvalid ), + .mem_axi_bready (mem_axi_bready ), + + .mem_axi_arvalid (mem_axi_arvalid ), + .mem_axi_arready (mem_axi_arready ), + .mem_axi_araddr (mem_axi_araddr ), + .mem_axi_arprot (mem_axi_arprot ), + + .mem_axi_rvalid (mem_axi_rvalid ), + .mem_axi_rready (mem_axi_rready ), + .mem_axi_rdata (mem_axi_rdata ) + ); + + picorv32_axi #( +`ifdef SP_TEST + .ENABLE_REGS_DUALPORT(0), +`endif + .ENABLE_MUL(1), + .ENABLE_IRQ(1) + ) uut ( + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_axi_awvalid(mem_axi_awvalid), + .mem_axi_awready(mem_axi_awready), + .mem_axi_awaddr (mem_axi_awaddr ), + .mem_axi_awprot (mem_axi_awprot ), + .mem_axi_wvalid (mem_axi_wvalid ), + .mem_axi_wready (mem_axi_wready ), + .mem_axi_wdata (mem_axi_wdata ), + .mem_axi_wstrb (mem_axi_wstrb ), + .mem_axi_bvalid (mem_axi_bvalid ), + .mem_axi_bready (mem_axi_bready ), + .mem_axi_arvalid(mem_axi_arvalid), + .mem_axi_arready(mem_axi_arready), + .mem_axi_araddr (mem_axi_araddr ), + .mem_axi_arprot (mem_axi_arprot ), + .mem_axi_rvalid (mem_axi_rvalid ), + .mem_axi_rready (mem_axi_rready ), + .mem_axi_rdata (mem_axi_rdata ), + .irq (irq ) + ); + + initial $readmemh("firmware/firmware.hex", mem.memory); + + integer cycle_counter; + always @(posedge clk) begin + cycle_counter <= resetn ? cycle_counter + 1 : 0; + if (resetn && trap) begin +`ifndef VERILATOR + repeat (10) @(posedge clk); +`endif + $display("TRAP after %1d clock cycles", cycle_counter); + $finish; + end + end +endmodule diff --git a/testbench.v b/testbench.v index af3156e..404c9c1 100644 --- a/testbench.v +++ b/testbench.v @@ -15,14 +15,6 @@ module testbench #( reg clk = 1; reg resetn = 0; - reg [31:0] irq; - wire trap; - - always @* begin - irq = 0; - irq[4] = &uut.picorv32_core.count_cycle[12:0]; - irq[5] = &uut.picorv32_core.count_cycle[15:0]; - end always #5 clk = ~clk; @@ -31,88 +23,6 @@ module testbench #( resetn <= 1; end - wire mem_axi_awvalid; - wire mem_axi_awready; - wire [31:0] mem_axi_awaddr; - wire [ 2:0] mem_axi_awprot; - - wire mem_axi_wvalid; - wire mem_axi_wready; - wire [31:0] mem_axi_wdata; - wire [ 3:0] mem_axi_wstrb; - - wire mem_axi_bvalid; - wire mem_axi_bready; - - wire mem_axi_arvalid; - wire mem_axi_arready; - wire [31:0] mem_axi_araddr; - wire [ 2:0] mem_axi_arprot; - - wire mem_axi_rvalid; - wire mem_axi_rready; - wire [31:0] mem_axi_rdata; - - axi4_memory #( - .AXI_TEST (AXI_TEST), - .VERBOSE (VERBOSE) - ) mem ( - .clk (clk ), - .mem_axi_awvalid (mem_axi_awvalid ), - .mem_axi_awready (mem_axi_awready ), - .mem_axi_awaddr (mem_axi_awaddr ), - .mem_axi_awprot (mem_axi_awprot ), - - .mem_axi_wvalid (mem_axi_wvalid ), - .mem_axi_wready (mem_axi_wready ), - .mem_axi_wdata (mem_axi_wdata ), - .mem_axi_wstrb (mem_axi_wstrb ), - - .mem_axi_bvalid (mem_axi_bvalid ), - .mem_axi_bready (mem_axi_bready ), - - .mem_axi_arvalid (mem_axi_arvalid ), - .mem_axi_arready (mem_axi_arready ), - .mem_axi_araddr (mem_axi_araddr ), - .mem_axi_arprot (mem_axi_arprot ), - - .mem_axi_rvalid (mem_axi_rvalid ), - .mem_axi_rready (mem_axi_rready ), - .mem_axi_rdata (mem_axi_rdata ) - ); - - picorv32_axi #( -`ifdef SP_TEST - .ENABLE_REGS_DUALPORT(0), -`endif - .ENABLE_MUL(1), - .ENABLE_IRQ(1) - ) uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_axi_awvalid(mem_axi_awvalid), - .mem_axi_awready(mem_axi_awready), - .mem_axi_awaddr (mem_axi_awaddr ), - .mem_axi_awprot (mem_axi_awprot ), - .mem_axi_wvalid (mem_axi_wvalid ), - .mem_axi_wready (mem_axi_wready ), - .mem_axi_wdata (mem_axi_wdata ), - .mem_axi_wstrb (mem_axi_wstrb ), - .mem_axi_bvalid (mem_axi_bvalid ), - .mem_axi_bready (mem_axi_bready ), - .mem_axi_arvalid(mem_axi_arvalid), - .mem_axi_arready(mem_axi_arready), - .mem_axi_araddr (mem_axi_araddr ), - .mem_axi_arprot (mem_axi_arprot ), - .mem_axi_rvalid (mem_axi_rvalid ), - .mem_axi_rready (mem_axi_rready ), - .mem_axi_rdata (mem_axi_rdata ), - .irq (irq ) - ); - - initial $readmemh("firmware/firmware.hex", mem.memory); - initial begin if ($test$plusargs("vcd")) begin $dumpfile("testbench.vcd"); @@ -123,13 +33,11 @@ module testbench #( $finish; end - integer cycle_counter; - always @(posedge clk) begin - cycle_counter <= resetn ? cycle_counter + 1 : 0; - if (resetn && trap) begin - repeat (10) @(posedge clk); - $display("TRAP after %1d clock cycles", cycle_counter); - $finish; - end - end + picorv32_wrapper #( + .AXI_TEST (AXI_TEST), + .VERBOSE (VERBOSE) + ) top ( + .clk (clk ), + .resetn (resetn) + ); endmodule |