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-rw-r--r--dhrystone/testbench.v19
1 files changed, 12 insertions, 7 deletions
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v
index a00e8f4..2d985d6 100644
--- a/dhrystone/testbench.v
+++ b/dhrystone/testbench.v
@@ -29,7 +29,9 @@ module testbench;
picorv32 #(
.BARREL_SHIFTER(1),
.ENABLE_MUL(1),
- .ENABLE_DIV(1)
+ .ENABLE_DIV(1),
+ .PROGADDR_RESET('h10000),
+ .STACKADDR('h10000)
) uut (
.clk (clk ),
.resetn (resetn ),
@@ -48,13 +50,16 @@ module testbench;
.mem_la_wstrb(mem_la_wstrb)
);
- reg [31:0] memory [0:64*1024/4-1];
+ reg [7:0] memory [0:256*1024-1];
initial $readmemh("dhry.hex", memory);
assign mem_ready = 1;
always @(posedge clk) begin
- mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx;
+ mem_rdata[ 7: 0] <= mem_la_read ? memory[mem_la_addr + 0] : 'bx;
+ mem_rdata[15: 8] <= mem_la_read ? memory[mem_la_addr + 1] : 'bx;
+ mem_rdata[23:16] <= mem_la_read ? memory[mem_la_addr + 2] : 'bx;
+ mem_rdata[31:24] <= mem_la_read ? memory[mem_la_addr + 3] : 'bx;
if (mem_la_write) begin
case (mem_la_addr)
32'h1000_0000: begin
@@ -64,10 +69,10 @@ module testbench;
`endif
end
default: begin
- if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
- if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
- if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
- if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
+ if (mem_la_wstrb[0]) memory[mem_la_addr + 0] <= mem_la_wdata[ 7: 0];
+ if (mem_la_wstrb[1]) memory[mem_la_addr + 1] <= mem_la_wdata[15: 8];
+ if (mem_la_wstrb[2]) memory[mem_la_addr + 2] <= mem_la_wdata[23:16];
+ if (mem_la_wstrb[3]) memory[mem_la_addr + 3] <= mem_la_wdata[31:24];
end
endcase
end