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-rw-r--r--picosoc/picosoc.v12
1 files changed, 11 insertions, 1 deletions
diff --git a/picosoc/picosoc.v b/picosoc/picosoc.v
index 353f2ef..9c5981e 100644
--- a/picosoc/picosoc.v
+++ b/picosoc/picosoc.v
@@ -25,6 +25,14 @@
`define PICORV32_REGS picosoc_regs
`endif
+`ifndef PICOSOC_MEM
+`define PICOSOC_MEM picosoc_mem
+`endif
+
+// this macro can be used to check if the verilog files in your
+// design are read in the correct order.
+`define PICOSOC_V
+
module picosoc (
input clk,
input resetn,
@@ -197,7 +205,9 @@ module picosoc (
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
- picosoc_mem #(.WORDS(MEM_WORDS)) memory (
+ `PICOSOC_MEM #(
+ .WORDS(MEM_WORDS)
+ ) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),