diff options
Diffstat (limited to 'scripts')
| -rw-r--r-- | scripts/synth_vivado_soc.v | 54 |
1 files changed, 33 insertions, 21 deletions
diff --git a/scripts/synth_vivado_soc.v b/scripts/synth_vivado_soc.v index b63c524..0b92d39 100644 --- a/scripts/synth_vivado_soc.v +++ b/scripts/synth_vivado_soc.v @@ -5,7 +5,7 @@ module test_soc ( input resetn, output trap, output [7:0] out_byte, - output out_byte_en, + output reg out_byte_en, output monitor_valid, output [31:0] monitor_addr, @@ -20,22 +20,29 @@ module test_soc ( wire [31:0] mem_wdata; wire [3:0] mem_wstrb; reg [31:0] mem_rdata; + wire mem_la_read; + wire mem_la_write; wire [31:0] mem_la_addr; + wire [31:0] mem_la_wdata; + wire [3:0] mem_la_wstrb; picorv32 uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_valid(mem_valid), - .mem_instr(mem_instr), - .mem_ready(mem_ready), - .mem_addr (mem_addr ), - .mem_wdata(mem_wdata), - .mem_wstrb(mem_wstrb), - .mem_rdata(mem_rdata), - .mem_la_read(mem_la_read), - .mem_la_addr(mem_la_addr) + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ), + .mem_la_read (mem_la_read ), + .mem_la_write(mem_la_write), + .mem_la_addr (mem_la_addr ), + .mem_la_wdata(mem_la_wdata), + .mem_la_wstrb(mem_la_wstrb) ); assign monitor_valid = mem_valid; @@ -46,17 +53,22 @@ module test_soc ( initial $readmemh("../firmware/firmware.hex", memory); assign mem_ready = 1; - assign out_byte = mem_wdata[7:0]; - assign out_byte_en = mem_addr == 32'h1000_0000; always @(posedge clk) begin - mem_rdata <= memory[mem_la_addr >> 2]; - if (mem_valid && (mem_addr >> 2) < MEM_SIZE) begin - if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; - if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; - if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; - if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; + out_byte_en <= 0; + if (mem_la_read) + mem_rdata <= memory[mem_la_addr >> 2]; + else + if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin + if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0]; + if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8]; + if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16]; + if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24]; + end + else + if (mem_la_write && mem_la_addr == 32'h1000_0000) begin + out_byte_en <= 1; end end endmodule |