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-rw-r--r--testbench.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/testbench.v b/testbench.v
index 6451252..eee2676 100644
--- a/testbench.v
+++ b/testbench.v
@@ -305,7 +305,7 @@ module axi4_memory #(
output reg tests_passed
);
- reg [31:0] memory [0:64*1024/4-1] /* verilator public */;
+ reg [31:0] memory [0:128*1024/4-1] /* verilator public */;
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
@@ -383,7 +383,7 @@ module axi4_memory #(
task handle_axi_rvalid; begin
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
- if (latched_raddr < 64*1024) begin
+ if (latched_raddr < 128*1024) begin
mem_axi_rdata <= memory[latched_raddr >> 2];
mem_axi_rvalid <= 1;
latched_raddr_en = 0;
@@ -396,7 +396,7 @@ module axi4_memory #(
task handle_axi_bvalid; begin
if (verbose)
$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
- if (latched_waddr < 64*1024) begin
+ if (latched_waddr < 128*1024) begin
if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
if (latched_wstrb[2]) memory[latched_waddr >> 2][23:16] <= latched_wdata[23:16];