| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | gitignore: update to ignore verilator artifacts | Austin Seipp | 2019-01-11 | 1 | -0/+1 |
| * | Add "make test_rvf" | Clifford Wolf | 2017-09-13 | 1 | -0/+1 |
| * | Add testbench_ez | Clifford Wolf | 2017-07-27 | 1 | -1/+1 |
| * | WIP: add WISHBONE testbench | Antony Pavlov | 2017-03-14 | 1 | -0/+2 |
| * | Renamed testbench_slow_mem to testbench_nola (no look ahead) | Clifford Wolf | 2016-09-04 | 1 | -0/+2 |
| * | Added tracer support (under construction) | Clifford Wolf | 2016-08-25 | 1 | -0/+1 |
| * | Using .vvp instead of .exe for iverilog executables | Clifford Wolf | 2016-05-04 | 1 | -6/+5 |
| * | Added "make clean" handling of riscv-gnu-toolchain-riscv32* directories | Clifford Wolf | 2016-04-09 | 1 | -0/+4 |
| * | Added "make check" | Clifford Wolf | 2015-10-14 | 1 | -0/+2 |
| * | Minor Makefile changes | Clifford Wolf | 2015-07-02 | 1 | -0/+1 |
| * | Added "make test_synth" | Clifford Wolf | 2015-06-30 | 1 | -0/+3 |
| * | Added "make test_sp" | Clifford Wolf | 2015-06-26 | 1 | -0/+1 |
| * | Test firmware refactoring | Clifford Wolf | 2015-06-26 | 1 | -1/+1 |
| * | Added basic IRQ support | Clifford Wolf | 2015-06-25 | 1 | -0/+2 |
| * | Major redesign of main FSM | Clifford Wolf | 2015-06-07 | 1 | -14/+18 |
| * | Improved Xilinx example | Clifford Wolf | 2015-06-06 | 1 | -4/+2 |
| * | Initial import | Clifford Wolf | 2015-06-06 | 1 | -0/+16 |
 |
index : picorv32 | |
| Fork of https://github.com/YosysHQ/picorv32. |
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path: root/.gitignore