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* Merge branch 'wishbone'Clifford Wolf2017-03-144-3/+548
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| * Fix indenting in wishbone codeClifford Wolf2017-03-142-139/+124
| * WIP: add WISHBONE testbenchAntony Pavlov2017-03-143-3/+361
| * WIP: add WISHBONE interconnect supportAntony Pavlov2017-03-141-0/+202
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* Rename "testbench_vcd" make target to "test_vcd", remove "view"Clifford Wolf2017-03-121-5/+2
* Fix in rvfi_mem_ handling (when compressed isa is enabled)Clifford Wolf2017-02-271-13/+12
* Add DEBUGNETS debug flagClifford Wolf2017-02-261-1/+6
* Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not remove...Clifford Wolf2017-02-211-2/+2
* Fix verilog code for modelsimClifford Wolf2017-02-172-5/+7
* Fix "mem_xfer is used before its declaration" warningClifford Wolf2017-02-111-1/+2
* Add scripts/presyn/ exampleClifford Wolf2017-02-099-0/+237
* Rename RVFI portsClifford Wolf2017-01-271-22/+22
* Fix README toolchain build instructionsClifford Wolf2017-01-161-1/+1
* Fix picorv32_axi STACKADDR default valueClifford Wolf2017-01-151-1/+1
* Merge pull request #28 from GuzTech/masterClifford Wolf2017-01-151-2/+4
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| * Add STACKADDR parameter to picorv32_axi moduleOguz Meteer2017-01-151-2/+4
* | Merge branch 'riscv-gnu-toolchain-update'Clifford Wolf2017-01-1513-96/+464
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| * Add newlib linker info to README fileClifford Wolf2017-01-152-4/+30
| * Added riscv.ld linker script (static entry point at 0x10000)Clifford Wolf2017-01-134-2/+292
| * Update riscv-gnu-toolchain to git rev 914224eClifford Wolf2017-01-134-11/+10
| * Some build fixes for new riscv-gnu-toolchainClifford Wolf2016-12-172-5/+5
| * Improved "git cherry-pick" for riscv-binutils-gdb a5971eca338Clifford Wolf2016-12-171-1/+1
| * Updated riscv-gnu-toolchain to git rev 34e199d + riscv-binutils-gdb commit a5...Clifford Wolf2016-12-171-1/+2
| * Updated riscv-gnu-toolchain to git rev e3e50c5Clifford Wolf2016-12-151-5/+5
| * Merge branch 'master' into riscv-gnu-toolchain-updateClifford Wolf2016-12-154-17/+22
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| * | Minor changes and build fixes for new riscv-gnu-toolchainClifford Wolf2016-12-103-13/+1
| * | assembler support for custom0 is deprecated, using cpp macros nowClifford Wolf2016-12-092-43/+107
| * | Added RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX Makefile variableClifford Wolf2016-12-091-13/+14
| * | Updated riscv-gnu-toolchainClifford Wolf2016-12-081-6/+5
* | | Added rvfi_mem interfaceClifford Wolf2016-12-201-4/+28
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* | Fixed some linter warnings in picorv32.vClifford Wolf2016-12-151-14/+14
* | Suppress iverilog warnings re parameters in "make test_synth"Clifford Wolf2016-12-152-1/+3
* | Fixed "make test_synth"Clifford Wolf2016-12-151-1/+2
* | Added rvfi_post_trapClifford Wolf2016-12-131-1/+3
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* Added cpu?_trap signals to tracecmp3.vClifford Wolf2016-12-031-0/+4
* Removed old scripts/smt2-bmc/Clifford Wolf2016-12-0310-1075/+0
* Fixed catching jumps to misaligned insnClifford Wolf2016-11-291-7/+9
* Renamed rvfi_opcode to rvfi_insnClifford Wolf2016-11-281-2/+2
* More RVFI bugfixesClifford Wolf2016-11-271-7/+18
* Minor RVFI bugfixClifford Wolf2016-11-241-1/+1
* Added RISC-V Formal Interfcae (RVFI)Clifford Wolf2016-11-232-2/+76
* Another bugfix regarding compressed ISA and unaligned insnsClifford Wolf2016-11-181-2/+2
* Added tracecmp3 smtbmc scriptClifford Wolf2016-11-163-0/+152
* Improved tomthumbtestgenClifford Wolf2016-10-248-33/+62
* Added scripts/tomthumbtestgenClifford Wolf2016-10-236-0/+183
* Improved READMEClifford Wolf2016-10-231-2/+4
* Added smtbmc axicheck2, improved axicheckClifford Wolf2016-10-016-20/+207
* Added smtbmc axicheckClifford Wolf2016-09-303-0/+201
* Fixed the nontrivial compressed ISA bug found by tracecmp2Clifford Wolf2016-09-161-3/+15
* Just COMPRESSED_ISA is enough to trigger the bugClifford Wolf2016-09-141-2/+2