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| author | Clifford Wolf <clifford@clifford.at> | 2016-12-15 12:51:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-12-15 13:11:26 +0100 |
| commit | 0bea8428f342a455c5ca720cbac02be111da7120 (patch) | |
| tree | 7c6a70312c6905117f16a20321d1c4aafc0a1748 | |
| parent | ca5702c75f50c2aba17d1495039fdcbab13f8987 (diff) | |
| download | picorv32-0bea8428f342a455c5ca720cbac02be111da7120.tar.gz picorv32-0bea8428f342a455c5ca720cbac02be111da7120.zip | |
Suppress iverilog warnings re parameters in "make test_synth"
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | testbench.v | 2 |
2 files changed, 3 insertions, 1 deletions
@@ -49,7 +49,7 @@ testbench_sp.vvp: testbench.v picorv32.v chmod -x testbench_sp.vvp testbench_synth.vvp: testbench.v synth.v - iverilog -o testbench_synth.vvp testbench.v synth.v + iverilog -o testbench_synth.vvp -DSYNTH_TEST testbench.v synth.v chmod -x testbench_synth.vvp synth.v: picorv32.v scripts/yosys/synth_sim.ys diff --git a/testbench.v b/testbench.v index 18cce40..84a2fd0 100644 --- a/testbench.v +++ b/testbench.v @@ -139,6 +139,7 @@ module picorv32_wrapper #( ); picorv32_axi #( +`ifndef SYNTH_TEST `ifdef SP_TEST .ENABLE_REGS_DUALPORT(0), `endif @@ -149,6 +150,7 @@ module picorv32_wrapper #( .ENABLE_DIV(1), .ENABLE_IRQ(1), .ENABLE_TRACE(1) +`endif ) uut ( .clk (clk ), .resetn (resetn ), |