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* Add spiflash testbench and add support for QSPI and DDR QSPI to SPI flash sim...Clifford Wolf2017-08-054-26/+609
* Change spiflash pin interfaces to support quad SPIClifford Wolf2017-08-045-51/+156
* Improve spiflash testbench and firmwareClifford Wolf2017-07-293-22/+80
* Add prefetching to spimemioClifford Wolf2017-07-291-1/+18
* Update spiflash READMEClifford Wolf2017-07-292-18/+27
* Add spiflash example projectClifford Wolf2017-07-299-0/+454
* Update READMEClifford Wolf2017-07-291-3/+9
* Add testbench_ezClifford Wolf2017-07-274-4/+100
* Update vivado evaluationsClifford Wolf2017-07-204-39/+53
* Suppress writes to cpuregs[0] to prevent confusionClifford Wolf2017-07-141-2/+2
* Fix scripts/torture gcc callsClifford Wolf2017-07-102-2/+2
* Remove some trailing whitespaceLarry Doolittle2017-06-139-11/+11
* Add rvfi_halt and rvfi_intr portsClifford Wolf2017-06-061-0/+4
* Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test benchClifford Wolf2017-05-273-3/+146
* Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal)Clifford Wolf2017-05-181-2/+2
* Fix decoding of C.ADDI instructionClifford Wolf2017-05-131-5/+3
* Add riscv-formal alu/regs blackboxingClifford Wolf2017-05-111-0/+14
* Fix decoding of illegal/reserved opcodes as other valid opcodesClifford Wolf2017-05-071-21/+29
* Update riscv-gnu-toolchain to git rev 4e51f26Clifford Wolf2017-05-052-3/+3
* Update riscv-gnu-toolchain to git rev 0c8f87dClifford Wolf2017-04-074-13/+14
* Merge pull request #40 from open-design/20170406.wishboneClifford Wolf2017-04-072-9/+25
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| * testbench_wb.v: unify verbose output with axi testbenchAntony Pavlov2017-04-062-9/+25
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* Merge pull request #39 from open-design/20170324.wishboneClifford Wolf2017-03-241-96/+11
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| * testbench_wb.v: drop unused stuffAntony Pavlov2017-03-171-96/+11
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* Add GIT_ENV Makefile variable (for things like http proxy settings)Clifford Wolf2017-03-151-2/+5
* Merge pull request #37 from open-design/20170315.testbenchesClifford Wolf2017-03-153-20/+19
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| * Makefile: use automatic variables in testbench rulesAntony Pavlov2017-03-151-10/+10
| * testbench.v: fix whitespacesAntony Pavlov2017-03-151-2/+2
| * testbench_wb.v: fix output stuffAntony Pavlov2017-03-151-8/+7
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* Merge branch 'wishbone'Clifford Wolf2017-03-144-3/+548
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| * Fix indenting in wishbone codeClifford Wolf2017-03-142-139/+124
| * WIP: add WISHBONE testbenchAntony Pavlov2017-03-143-3/+361
| * WIP: add WISHBONE interconnect supportAntony Pavlov2017-03-141-0/+202
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* Rename "testbench_vcd" make target to "test_vcd", remove "view"Clifford Wolf2017-03-121-5/+2
* Fix in rvfi_mem_ handling (when compressed isa is enabled)Clifford Wolf2017-02-271-13/+12
* Add DEBUGNETS debug flagClifford Wolf2017-02-261-1/+6
* Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not remove...Clifford Wolf2017-02-211-2/+2
* Fix verilog code for modelsimClifford Wolf2017-02-172-5/+7
* Fix "mem_xfer is used before its declaration" warningClifford Wolf2017-02-111-1/+2
* Add scripts/presyn/ exampleClifford Wolf2017-02-099-0/+237
* Rename RVFI portsClifford Wolf2017-01-271-22/+22
* Fix README toolchain build instructionsClifford Wolf2017-01-161-1/+1
* Fix picorv32_axi STACKADDR default valueClifford Wolf2017-01-151-1/+1
* Merge pull request #28 from GuzTech/masterClifford Wolf2017-01-151-2/+4
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| * Add STACKADDR parameter to picorv32_axi moduleOguz Meteer2017-01-151-2/+4
* | Merge branch 'riscv-gnu-toolchain-update'Clifford Wolf2017-01-1513-96/+464
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| * Add newlib linker info to README fileClifford Wolf2017-01-152-4/+30
| * Added riscv.ld linker script (static entry point at 0x10000)Clifford Wolf2017-01-134-2/+292
| * Update riscv-gnu-toolchain to git rev 914224eClifford Wolf2017-01-134-11/+10
| * Some build fixes for new riscv-gnu-toolchainClifford Wolf2016-12-172-5/+5
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