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* Refactoring of IRQ handlingClifford Wolf2015-06-265-114/+168
* Improvements in README.mdClifford Wolf2015-06-251-24/+23
* Added basic IRQ supportClifford Wolf2015-06-257-19/+546
* Added simple icestorm script (not a real example yet)Clifford Wolf2015-06-222-0/+7
* Updated Vivado SoC exampleClifford Wolf2015-06-105-18/+47
* Makefile for Vivado scriptsClifford Wolf2015-06-0910-23/+58
* More TodosClifford Wolf2015-06-091-0/+3
* Removed unnecessary "jal" complexityClifford Wolf2015-06-091-4/+1
* Small improvements in vivado_soc demoClifford Wolf2015-06-081-5/+4
* Added osu018 yosys synthesis scriptClifford Wolf2015-06-086-1/+10
* Refactored instruction decoderClifford Wolf2015-06-083-174/+223
* Improved timing for "decoded_imm_uj"Clifford Wolf2015-06-071-4/+3
* README UpdatesClifford Wolf2015-06-071-2/+6
* Added support for dual-port register fileClifford Wolf2015-06-072-21/+74
* minor optimizationsClifford Wolf2015-06-071-5/+7
* Improved "decoder_trigger" handlingClifford Wolf2015-06-071-14/+11
* Added look-ahead write interfaceClifford Wolf2015-06-073-58/+73
* Major redesign of main FSMClifford Wolf2015-06-078-303/+287
* Using libc assembler code in dhrystone stdlib.cClifford Wolf2015-06-075-4/+606
* Updated CPI table in READMEClifford Wolf2015-06-061-9/+11
* Updated READMEClifford Wolf2015-06-061-6/+16
* Added insn timing hack to dryhstone testbenchClifford Wolf2015-06-061-1/+15
* Added memory "look-ahead" read interfaceClifford Wolf2015-06-063-28/+36
* Improved Xilinx exampleClifford Wolf2015-06-066-10/+69
* Faster memory model in dhrystone testbenchClifford Wolf2015-06-061-18/+18
* Improved AXI testsClifford Wolf2015-06-062-73/+90
* Added license info to READMEClifford Wolf2015-06-061-0/+3
* Improved AXI Interface TestbenchClifford Wolf2015-06-062-35/+110
* Initial importClifford Wolf2015-06-0660-0/+6250