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* Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal)Clifford Wolf2017-05-181-2/+2
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* Fix decoding of C.ADDI instructionClifford Wolf2017-05-131-5/+3
| | | | | See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts for discussion. There was a bug in the ISA manual.
* Add riscv-formal alu/regs blackboxingClifford Wolf2017-05-111-0/+14
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* Fix decoding of illegal/reserved opcodes as other valid opcodesClifford Wolf2017-05-071-21/+29
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* Update riscv-gnu-toolchain to git rev 4e51f26Clifford Wolf2017-05-052-3/+3
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* Update riscv-gnu-toolchain to git rev 0c8f87dClifford Wolf2017-04-074-13/+14
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* Merge pull request #40 from open-design/20170406.wishboneClifford Wolf2017-04-072-9/+25
|\ | | | | testbench_wb.v: unify verbose output with axi testbench
| * testbench_wb.v: unify verbose output with axi testbenchAntony Pavlov2017-04-062-9/+25
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unification of testbench output makes it possible to use the diff utility for comparing testbench instruction traces. Alas the testbench and testbench_wb traces are differ because of interrupts, e.g. picorv32$ make testbench_wb.vvp iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v chmod -x testbench_wb.vvp picorv32$ make testbench.vvp iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v chmod -x testbench.vvp picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log --- /tmp/testbench.log 2017-04-06 06:56:06.079804549 +0300 +++ /tmp/testbench_wb.log 2017-04-06 06:55:58.763485130 +0300 @@ -850,7 +850,7 @@ RD: ADDR=000056a0 DATA=00000013 INSN RD: ADDR=000056a4 DATA=fff00113 INSN RD: ADDR=000056a8 DATA=00000013 INSN -RD: ADDR=000056ac DATA=14208463 INSN <--- testbench: no interrupt -RD: ADDR=000056b0 DATA=00120213 INSN -RD: ADDR=000056b4 DATA=00200293 INSN -RD: ADDR=000056b8 DATA=fe5212e3 INSN +RD: ADDR=00000010 DATA=0200a10b INSN <--- testbench_wb: interrupt +RD: ADDR=00000014 DATA=0201218b INSN +RD: ADDR=00000018 DATA=000000b7 INSN +RD: ADDR=0000001c DATA=16008093 INSN Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* Merge pull request #39 from open-design/20170324.wishboneClifford Wolf2017-03-241-96/+11
|\ | | | | testbench_wb.v: drop unused stuff
| * testbench_wb.v: drop unused stuffAntony Pavlov2017-03-171-96/+11
|/ | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* Add GIT_ENV Makefile variable (for things like http proxy settings)Clifford Wolf2017-03-151-2/+5
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* Merge pull request #37 from open-design/20170315.testbenchesClifford Wolf2017-03-153-20/+19
|\ | | | | 20170315.testbenches
| * Makefile: use automatic variables in testbench rulesAntony Pavlov2017-03-151-10/+10
| | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
| * testbench.v: fix whitespacesAntony Pavlov2017-03-151-2/+2
| | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
| * testbench_wb.v: fix output stuffAntony Pavlov2017-03-151-8/+7
|/ | | | | | | | | | | | | | | This patch fixes wishbone testbench output issue: 'DNNE' instead of 'DONE', i.e. Cycle counter ......... 546536 Instruction counter .... 69770 CPI: 7.83 DNNE ------------------------------------------------------------ EBREAK instruction at 0x000006C4 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* Merge branch 'wishbone'Clifford Wolf2017-03-144-3/+548
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| * Fix indenting in wishbone codeClifford Wolf2017-03-142-139/+124
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| * WIP: add WISHBONE testbenchAntony Pavlov2017-03-143-3/+361
| | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
| * WIP: add WISHBONE interconnect supportAntony Pavlov2017-03-141-0/+202
|/ | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
* Rename "testbench_vcd" make target to "test_vcd", remove "view"Clifford Wolf2017-03-121-5/+2
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* Fix in rvfi_mem_ handling (when compressed isa is enabled)Clifford Wolf2017-02-271-13/+12
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* Add DEBUGNETS debug flagClifford Wolf2017-02-261-1/+6
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* Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not ↵Clifford Wolf2017-02-211-2/+2
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* Fix verilog code for modelsimClifford Wolf2017-02-172-5/+7
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* Fix "mem_xfer is used before its declaration" warningClifford Wolf2017-02-111-1/+2
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* Add scripts/presyn/ exampleClifford Wolf2017-02-099-0/+237
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* Rename RVFI portsClifford Wolf2017-01-271-22/+22
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* Fix README toolchain build instructionsClifford Wolf2017-01-161-1/+1
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* Fix picorv32_axi STACKADDR default valueClifford Wolf2017-01-151-1/+1
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* Merge pull request #28 from GuzTech/masterClifford Wolf2017-01-151-2/+4
|\ | | | | Add STACKADDR parameter to picorv32_axi module
| * Add STACKADDR parameter to picorv32_axi moduleOguz Meteer2017-01-151-2/+4
| | | | | | | | Signed-off-by: Oguz Meteer <info@guztech.nl>
* | Merge branch 'riscv-gnu-toolchain-update'Clifford Wolf2017-01-1513-96/+464
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| * Add newlib linker info to README fileClifford Wolf2017-01-152-4/+30
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| * Added riscv.ld linker script (static entry point at 0x10000)Clifford Wolf2017-01-134-2/+292
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| * Update riscv-gnu-toolchain to git rev 914224eClifford Wolf2017-01-134-11/+10
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| * Some build fixes for new riscv-gnu-toolchainClifford Wolf2016-12-172-5/+5
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| * Improved "git cherry-pick" for riscv-binutils-gdb a5971eca338Clifford Wolf2016-12-171-1/+1
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| * Updated riscv-gnu-toolchain to git rev 34e199d + riscv-binutils-gdb commit ↵Clifford Wolf2016-12-171-1/+2
| | | | | | | | a5971eca338
| * Updated riscv-gnu-toolchain to git rev e3e50c5Clifford Wolf2016-12-151-5/+5
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| * Merge branch 'master' into riscv-gnu-toolchain-updateClifford Wolf2016-12-154-17/+22
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| * | Minor changes and build fixes for new riscv-gnu-toolchainClifford Wolf2016-12-103-13/+1
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| * | assembler support for custom0 is deprecated, using cpp macros nowClifford Wolf2016-12-092-43/+107
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| * | Added RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX Makefile variableClifford Wolf2016-12-091-13/+14
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| * | Updated riscv-gnu-toolchainClifford Wolf2016-12-081-6/+5
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* | | Added rvfi_mem interfaceClifford Wolf2016-12-201-4/+28
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* | Fixed some linter warnings in picorv32.vClifford Wolf2016-12-151-14/+14
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* | Suppress iverilog warnings re parameters in "make test_synth"Clifford Wolf2016-12-152-1/+3
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* | Fixed "make test_synth"Clifford Wolf2016-12-151-1/+2
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* | Added rvfi_post_trapClifford Wolf2016-12-131-1/+3
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* Added cpu?_trap signals to tracecmp3.vClifford Wolf2016-12-031-0/+4
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