aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
* Add PicoSoC IceBreaker demoClifford Wolf2018-08-187-8/+341
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #79 from olofk/irqconfigClifford Wolf2018-08-181-2/+4
|\ | | | | Expose ENABLE_IRQ_QREGS and PROGADDR_IRQ from picosoc.v
| * Expose ENABLE_IRQ_QREGS and PROGADDR_IRQ from picosoc.vOlof Kindgren2018-08-161-2/+4
|/
* PicoSoC: Use RDSR1+RDCR1+WRR instead of RDAR+WRARClifford Wolf2018-08-161-6/+41
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update riscv-gnu-toolchainClifford Wolf2018-08-142-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add rs232 decode to picosoc hx8kdemo test benchClifford Wolf2018-08-141-0/+39
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix picosoc quad spi mode (flashio_worker must be multiple of 4 bytes)Clifford Wolf2018-08-141-1/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve picosoc demo firmware, picosoc firmware build fixesClifford Wolf2018-08-143-19/+59
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #61 from mmicko/linker-scriptClifford Wolf2018-08-143-12/+74
|\ | | | | Created lds file (section mapping) and init for data and bss sections
| * Created lfs file (section mappint) and init for data and bss sectionsMiodrag Milanovic2018-04-163-12/+74
| |
* | Merge pull request #74 from olofk/picosoc-fusesoc_v2Clifford Wolf2018-08-143-0/+82
|\ \ | | | | | | Picosoc fusesoc v2
| * | Add FuseSoC .core file for hx8kdemoOlof Kindgren2018-07-271-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | The core file specifies targets for FPGA implementation (fusesoc build hx8kdemo) and simulation (fusesoc run --tool=<tool> --target=sim hx8kdemo --firmware=path/to/firmware.he). Simulation has been tested successfully with icarus, modelsim and xsim
| * | Add FuseSoC .core file for picosocOlof Kindgren2018-07-271-0/+23
| | | | | | | | | | | | | | | This allows other cores to depend on the generic parts of picosoc and use that as a base design.
| * | Add FuseSoC .core file for SPI Flash modelOlof Kindgren2018-07-261-0/+24
|/ / | | | | | | | | | | | | | | | | | | This allows other cores to depend on spiflash. Can also be used to run the spiflash testbench with fusesoc run --tool=<tool> spiflash --firmware=path/to/firmware.hex This has been tested with icarus, modelsim and xsim. Fails with isim If --tool is left out, icarus will be used as default
* | Update riscv-gnu-toolchain to cb6b34bClifford Wolf2018-06-292-5/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix showtrace.py for changed objdump output formatClifford Wolf2018-05-252-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix "make testbench_verilator" bugClifford Wolf2018-05-251-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve testbench_verilatorClifford Wolf2018-05-252-19/+30
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "make test_verilator"Clifford Wolf2018-05-251-0/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #69 from olofk/picosoc_regs_v3Clifford Wolf2018-05-191-0/+2
|\ \ | | | | | | Bypass picosoc compile order check if PICORV32_REGS is defined.
| * | Bypass picosoc compile order check if PICORV32_REGS is defined.Olof Kindgren2018-05-181-0/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | Previously, picosoc.v needed to be sourced before picorv32.v to ensure that the PICORV32_REGS `define (used to select implementation for the register file) was set to picosoc_regs This allows for overriding PICORV32_REGS, e.g. by setting it externally in the EDA tool invocation. In this case, the compile order between picorv32.v and picosoc.v is not important. Note: This change will break the safety check if PICORV32_REGS is defined between sourcing picorv32.v and picosoc.v
* | Merge pull request #66 from olofk/spiflash-plusargClifford Wolf2018-05-151-1/+4
|\ \ | | | | | | spiflash: Allow setting firmware from plusarg
| * | spiflash: Allow setting firmware from plusargOlof Kindgren2018-05-151-1/+4
|/ /
* | Merge pull request #63 from olofk/fix-spiflash_tbClifford Wolf2018-05-121-6/+6
|\ \ | | | | | | Fix spiflash_tb
| * | Fix spiflash_tbOlof Kindgren2018-05-111-6/+6
|/ / | | | | | | | | | | Update expected two first Flash words to reflect changes in start.s Add dummy SPI cycles to account for latency
* / Fix miscellaneous typos in documentationLarry Doolittle2018-04-174-4/+4
|/
* Merge pull request #59 from tinyfpga/masterClifford Wolf2018-04-081-0/+2
|\ | | | | add .data and .bss segments to picosoc
| * add .data and .bss segments to picosocLuke Valenty2018-04-071-0/+2
|/ | | added .data and .bss segments to picosoc firmware linker script so that static variables may be used.
* Update riscv-gnu-toolchain to 1b80cbeClifford Wolf2018-04-038-188/+334
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #56 from olofk/fusesocClifford Wolf2018-03-052-0/+105
|\ | | | | Verilator testbench and FuseSoC support
| * Add FuseSoC core fileOlof Kindgren2018-03-041-0/+78
| |
| * Add verilator testbenchOlof Kindgren2018-03-041-0/+27
|/
* Merge pull request #54 from thoughtpolice/misc-fixesClifford Wolf2018-02-163-5/+5
|\ | | | | Small fixes to the IceStorm scripts
| * scripts/icestorm: use 'yosys-config' to find data directoryAustin Seipp2018-02-141-2/+2
| | | | | | | | | | | | | | | | | | This fixes the icestorm script to query yosys-config itself for the right data directory. Not only does this fix installs where yosys was not installed into /usr/local, it also ensures Icarus picks up a data directory consistent with the version of yosys that you're using. Signed-off-by: Austin Seipp <aseipp@pobox.com>
| * scripts: remove old -m32 argument to riscv-gccAustin Seipp2018-02-143-3/+3
|/ | | | | | See also 55da6c7cd1f5ad798bfa0f52989434486c03b31b Signed-off-by: Austin Seipp <aseipp@pobox.com>
* Merge pull request #52 from olofk/testbench_wb_fixesClifford Wolf2017-12-311-1/+26
|\ | | | | Testbench wb fixes
| * testbench_wb: Add proper attribution for wb_ram moduleOlof Kindgren2017-12-271-0/+19
| |
| * testbench_wb: Load firmware with plusarg instead of parameterOlof Kindgren2017-12-271-1/+7
|/
* Update riscv-gnu-toolchain to bf5697aClifford Wolf2017-11-193-4/+4
|
* Fix picosoc hx8kdemo_tbClifford Wolf2017-11-111-1/+1
|
* Add missing "volatile" to "asm" statementsClifford Wolf2017-10-302-4/+4
|
* Update evaluation results to Vivado 2017.3Clifford Wolf2017-10-212-11/+11
|
* Update riscv-gnu-toolchain to git rev e9f5458Clifford Wolf2017-10-192-3/+3
|
* Update riscv-formal altops bitmasksClifford Wolf2017-10-071-8/+8
|
* Fix bug in picorv32_pcpi_div, Add RISCV_FORMAL_ALTOPS supportClifford Wolf2017-10-061-2/+23
|
* Add PICORV32_REGS mechanism for ASIC sram instantiationClifford Wolf2017-10-014-13/+130
|
* Improve PicoSoC overview.svgClifford Wolf2017-09-221-4/+94
|
* Enable a bunch of PicoRV32 features in PicoSoCClifford Wolf2017-09-226-23/+139
|
* Silenced some warnings when ENABLE_MUL but not ENABLE_PCPIClifford Wolf2017-09-221-2/+2
|
* Update PicoSoC READMEClifford Wolf2017-09-211-7/+23
|
generated by cgit (git 2.34.1) at 2024-07-05 21:17:41 +0000