picorv32 - Fork of https://github.com/YosysHQ/picorv32.

	Commit message (Expand)	Author	Age	Files	Lines
*	Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench	Clifford Wolf	2017-05-27	3	-3/+146
*	Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal)	Clifford Wolf	2017-05-18	1	-2/+2
*	Fix decoding of C.ADDI instruction	Clifford Wolf	2017-05-13	1	-5/+3
*	Add riscv-formal alu/regs blackboxing	Clifford Wolf	2017-05-11	1	-0/+14
*	Fix decoding of illegal/reserved opcodes as other valid opcodes	Clifford Wolf	2017-05-07	1	-21/+29
*	Update riscv-gnu-toolchain to git rev 4e51f26	Clifford Wolf	2017-05-05	2	-3/+3
*	Update riscv-gnu-toolchain to git rev 0c8f87d	Clifford Wolf	2017-04-07	4	-13/+14
*	Merge pull request #40 from open-design/20170406.wishbone	Clifford Wolf	2017-04-07	2	-9/+25
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\| *	testbench_wb.v: unify verbose output with axi testbench	Antony Pavlov	2017-04-06	2	-9/+25
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*	Merge pull request #39 from open-design/20170324.wishbone	Clifford Wolf	2017-03-24	1	-96/+11
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\| *	testbench_wb.v: drop unused stuff	Antony Pavlov	2017-03-17	1	-96/+11
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*	Add GIT_ENV Makefile variable (for things like http proxy settings)	Clifford Wolf	2017-03-15	1	-2/+5
*	Merge pull request #37 from open-design/20170315.testbenches	Clifford Wolf	2017-03-15	3	-20/+19
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\| *	Makefile: use automatic variables in testbench rules	Antony Pavlov	2017-03-15	1	-10/+10
\| *	testbench.v: fix whitespaces	Antony Pavlov	2017-03-15	1	-2/+2
\| *	testbench_wb.v: fix output stuff	Antony Pavlov	2017-03-15	1	-8/+7
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*	Merge branch 'wishbone'	Clifford Wolf	2017-03-14	4	-3/+548
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\| *	Fix indenting in wishbone code	Clifford Wolf	2017-03-14	2	-139/+124
\| *	WIP: add WISHBONE testbench	Antony Pavlov	2017-03-14	3	-3/+361
\| *	WIP: add WISHBONE interconnect support	Antony Pavlov	2017-03-14	1	-0/+202
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*	Rename "testbench_vcd" make target to "test_vcd", remove "view"	Clifford Wolf	2017-03-12	1	-5/+2
*	Fix in rvfi_mem_ handling (when compressed isa is enabled)	Clifford Wolf	2017-02-27	1	-13/+12
*	Add DEBUGNETS debug flag	Clifford Wolf	2017-02-26	1	-1/+6
*	Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not remove...	Clifford Wolf	2017-02-21	1	-2/+2
*	Fix verilog code for modelsim	Clifford Wolf	2017-02-17	2	-5/+7
*	Fix "mem_xfer is used before its declaration" warning	Clifford Wolf	2017-02-11	1	-1/+2
*	Add scripts/presyn/ example	Clifford Wolf	2017-02-09	9	-0/+237
*	Rename RVFI ports	Clifford Wolf	2017-01-27	1	-22/+22
*	Fix README toolchain build instructions	Clifford Wolf	2017-01-16	1	-1/+1
*	Fix picorv32_axi STACKADDR default value	Clifford Wolf	2017-01-15	1	-1/+1
*	Merge pull request #28 from GuzTech/master	Clifford Wolf	2017-01-15	1	-2/+4
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\| *	Add STACKADDR parameter to picorv32_axi module	Oguz Meteer	2017-01-15	1	-2/+4
* \|	Merge branch 'riscv-gnu-toolchain-update'	Clifford Wolf	2017-01-15	13	-96/+464
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\| *	Add newlib linker info to README file	Clifford Wolf	2017-01-15	2	-4/+30
\| *	Added riscv.ld linker script (static entry point at 0x10000)	Clifford Wolf	2017-01-13	4	-2/+292
\| *	Update riscv-gnu-toolchain to git rev 914224e	Clifford Wolf	2017-01-13	4	-11/+10
\| *	Some build fixes for new riscv-gnu-toolchain	Clifford Wolf	2016-12-17	2	-5/+5
\| *	Improved "git cherry-pick" for riscv-binutils-gdb a5971eca338	Clifford Wolf	2016-12-17	1	-1/+1
\| *	Updated riscv-gnu-toolchain to git rev 34e199d + riscv-binutils-gdb commit a5...	Clifford Wolf	2016-12-17	1	-1/+2
\| *	Updated riscv-gnu-toolchain to git rev e3e50c5	Clifford Wolf	2016-12-15	1	-5/+5
\| *	Merge branch 'master' into riscv-gnu-toolchain-update	Clifford Wolf	2016-12-15	4	-17/+22
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\| * \|	Minor changes and build fixes for new riscv-gnu-toolchain	Clifford Wolf	2016-12-10	3	-13/+1
\| * \|	assembler support for custom0 is deprecated, using cpp macros now	Clifford Wolf	2016-12-09	2	-43/+107
\| * \|	Added RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX Makefile variable	Clifford Wolf	2016-12-09	1	-13/+14
\| * \|	Updated riscv-gnu-toolchain	Clifford Wolf	2016-12-08	1	-6/+5
* \| \|	Added rvfi_mem interface	Clifford Wolf	2016-12-20	1	-4/+28
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* \|	Fixed some linter warnings in picorv32.v	Clifford Wolf	2016-12-15	1	-14/+14
* \|	Suppress iverilog warnings re parameters in "make test_synth"	Clifford Wolf	2016-12-15	2	-1/+3
* \|	Fixed "make test_synth"	Clifford Wolf	2016-12-15	1	-1/+2
* \|	Added rvfi_post_trap	Clifford Wolf	2016-12-13	1	-1/+3
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