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read_verilog main.v
read_verilog ../../picorv32.v
rename main main_a
chparam -set ENABLE_REGS_DUALPORT 0 \
-set TWO_STAGE_SHIFT 0 \
-set TWO_CYCLE_COMPARE 0 \
-set TWO_CYCLE_ALU 0 main_a
hierarchy -top main_a
proc
opt
memory -nordff -nomap
flatten
opt
write_smt2 -bv -mem -regs async_a.smt2
design -reset
read_verilog main.v
read_verilog ../../picorv32.v
rename main main_b
chparam -set ENABLE_REGS_DUALPORT 1 \
-set TWO_STAGE_SHIFT 1 \
-set TWO_CYCLE_COMPARE 1 \
-set TWO_CYCLE_ALU 1 main_b
hierarchy -top main_b
proc
opt
memory -nordff -nomap
flatten
opt
write_smt2 -bv -mem -regs async_b.smt2
design -reset
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