blob: 67b49deca17895aa44b9790ae5c2c7bb8fe4884c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
read_verilog mem_equiv.v
read_verilog ../../picorv32.v
rename main main_a
chparam -set ENABLE_REGS_DUALPORT 0 \
-set TWO_STAGE_SHIFT 0 \
-set TWO_CYCLE_COMPARE 0 \
-set TWO_CYCLE_ALU 0 main_a
hierarchy -top main_a
proc
opt
memory -nordff -nomap
flatten
opt
write_smt2 -bv -mem -regs mem_equiv_a.smt2
design -reset
read_verilog mem_equiv.v
read_verilog ../../picorv32.v
rename main main_b
chparam -set ENABLE_REGS_DUALPORT 1 \
-set TWO_STAGE_SHIFT 1 \
-set TWO_CYCLE_COMPARE 1 \
-set TWO_CYCLE_ALU 1 main_b
hierarchy -top main_b
proc
opt
memory -nordff -nomap
flatten
opt
write_smt2 -bv -mem -regs mem_equiv_b.smt2
design -reset
|