1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
read_verilog ../../picorv32.v read_xdc synth_speed.xdc synth_design -part xc7k70t-fbg676 -top picorv32_axi opt_design place_design phys_opt_design route_design report_utilization report_timing write_verilog -force synth_speed.v