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+<!-- This document was automatically generated with bibtex2html 1.99
+ (see http://www.lri.fr/~filliatr/bibtex2html/),
+ with the following command:
+ bibtex2html -o blog/templates/papers -use-keys -dl -linebreak -noabstract -nokeywords -nobibsource -nofooter -nodoc --named-field url_video video --named-field url_tex tex --named-field url_slides slides --named-field url_press press --named-field url_poster poster --named-field url_manuscript pdf --named-field url_blog_post blog --named-field url_artifact artifact blog/yann.bib -->
+
+
+<dl>
+
+<dt>
+<b><a name="OOPSLA&nbsp;&#39;21">OOPSLA&nbsp;&#39;21</a></b>
+</dt>
+<dd>
+<b>Yann Herklotz</b>, James&nbsp;D. Pollard, Nadesh Ramanathan, and John Wickerson.
+ Formal verification of high-level synthesis.
+ volume&nbsp;5, New York, NY, USA, 11 2021. Association for Computing
+ Machinery.<br />
+<b>&nbsp;<a href="/papers/fvhls_oopsla21.pdf">pdf</a>&nbsp;</b>
+
+</dd>
+
+
+<dt>
+<b><a name="FCCM&nbsp;&#39;21">FCCM&nbsp;&#39;21</a></b>
+</dt>
+<dd>
+<b>Yann Herklotz</b>, Zewei Du, Nadesh Ramanathan, and John Wickerson.
+ An empirical study of the reliability of high-level synthesis tools.
+ In <em>29th IEEE Annual Int. Symp. on Field-Programmable Custom
+ Computing Machines</em>, 2021.<br />
+[&nbsp;<a href="http://dx.doi.org/10.1109/FCCM51124.2021.00034">DOI</a>&nbsp;|
+<a href="https://github.com/ymherklotz/fuzzing-hls">artifact</a>&nbsp;|
+<a href="/papers/esrhls_fccm2021.pdf">pdf</a>&nbsp;]
+
+</dd>
+
+
+<dt>
+<b><a name="FPGA&nbsp;&#39;20">FPGA&nbsp;&#39;20</a></b>
+</dt>
+<dd>
+<b>Yann Herklotz</b> and John Wickerson.
+ Finding and understanding bugs in FPGA synthesis tools.
+ In <em>ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays</em>,
+ 2020.<br />
+[&nbsp;<a href="http://dx.doi.org/10.1145/3373087.3375310">DOI</a>&nbsp;|
+<a href="https://github.com/ymherklotz/verismith">artifact</a>&nbsp;|
+<a href="/blog/2019-06-19-verismith.html">blog</a>&nbsp;|
+<a href="/papers/fubfst_fpga2020.pdf">pdf</a>&nbsp;|
+<a href="/docs/msrphd2019/verismith_poster.pdf">poster</a>&nbsp;|
+<a href="/docs/fpga2020/verismith_slides.pdf">slides</a>&nbsp;]
+
+</dd>
+</dl>