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authorYann Herklotz <ymh15@ic.ac.uk>2022-03-31 10:42:34 +0000
committernode <node@git-bridge-prod-0>2022-03-31 10:43:54 +0000
commit4089b9d1fb7f7e67f34c4a38e987dfc52cad96bc (patch)
tree452ca5b700487d5054350da72be4f0ee2ea4852d
parent5b8b6ae5f11b85d81fc74b7fc89c4c392a4f16bc (diff)
downloadfccm22_rsvhls-4089b9d1fb7f7e67f34c4a38e987dfc52cad96bc.tar.gz
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Update on Overleaf.
-rw-r--r--verified_resource_sharing.tex5
1 files changed, 3 insertions, 2 deletions
diff --git a/verified_resource_sharing.tex b/verified_resource_sharing.tex
index e441688..9933ae8 100644
--- a/verified_resource_sharing.tex
+++ b/verified_resource_sharing.tex
@@ -66,6 +66,7 @@ escapeinside=||,
\newcommand\MP[2][]{\st{#1}\Comment{blue!50!magenta}{MP}{#2}}
\newcommand\JWchanged[1]{\textcolor{red!75!black}{#1}}
+\newcommand\YHchanged[1]{\textcolor{blue!50!green}{#1}}
\newcommand\vericert{Vericert}
\newcommand\vericertfun{Vericert-Fun}
@@ -122,8 +123,8 @@ Developing software within a proof assistant like Coq is widely held to be the g
It transforms its input through a series of ten intermediate languages before generating the final output.
%This design ensures that each individual pass remains relatively simple and hence feasible to prove correct.
The correctness proof of the entire compiler is formed by composing the correctness proofs of each of those passes.
-That the Csmith compiler testing tool~\cite{csmith} has found hundreds of bugs in GCC and LLVM but none in (the verified parts of) CompCert is a testament to the reliability of this development approach.
-That said, we cannot guarantee \vericertfun{} designs will never go wrong, because of fallible components not covered by the theorem, such as the synthesis toolchain~\cite{verismith} and the FPGA itself.
+\YHchanged{That the Csmith compiler testing tool}~\cite{csmith} has found hundreds of bugs in GCC and LLVM but none in (the verified parts of) CompCert is a testament to the reliability of this development approach.
+\YHchanged{However, we} cannot guarantee \vericertfun{} designs will never go wrong, because of fallible components not covered by the theorem, such as the synthesis toolchain~\cite{verismith} and the FPGA itself.
\paragraph{The \vericert{} verified HLS tool}