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| author | John Wickerson <j.wickerson@imperial.ac.uk> | 2021-12-17 10:44:35 +0000 |
|---|---|---|
| committer | node <node@git-bridge-prod-0> | 2021-12-17 11:38:29 +0000 |
| commit | b680c949ba68dffdf4347f86cd2f780178b3d1f4 (patch) | |
| tree | bc0936bf250770a83ee7466f88d95d6982a2310d | |
| parent | ed15ae209caecdaeeee14c27348ab3a314e71995 (diff) | |
| download | fccm22_rsvhls-b680c949ba68dffdf4347f86cd2f780178b3d1f4.tar.gz fccm22_rsvhls-b680c949ba68dffdf4347f86cd2f780178b3d1f4.zip | |
Update on Overleaf.
| -rw-r--r-- | verified_resource_sharing.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/verified_resource_sharing.tex b/verified_resource_sharing.tex index 9470a18..4c104ba 100644 --- a/verified_resource_sharing.tex +++ b/verified_resource_sharing.tex @@ -364,7 +364,7 @@ A few points that we might want to address at some point: \item What is needed for the correctness proof? (Semantics for C, semantics for Verilog, ...) -\item We considered having multiple Verilog modules, which would be more idiomatic, but this would require more invasive changes to the semantics. +\item We considered having multiple Verilog modules; this would be more idiomatic, but this would require more invasive changes to the semantics. \end{itemize} |