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| -rw-r--r-- | references.bib | 37 |
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diff --git a/references.bib b/references.bib index cec647e..4a2b791 100644 --- a/references.bib +++ b/references.bib @@ -20,6 +20,12 @@ url = {https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html}, } +@misc{vericertfun-github, + author = {{Withheld for blind review}}, + title = {Public Github repository for Vericert-Fun}, + year = 2022, +} + @misc{xilinx_vitis, publisher = {Xilinx Inc.}, title = {Vitis HLS}, @@ -405,3 +411,34 @@ year = {2016}, pages = {1-4}, doi = {10.1109/FPL.2013.6645550} } + +@article{huang+15, + author = {Qijing Huang and + Ruolong Lian and + Andrew Canis and + Jongsok Choi and + Ryan Xi and + Nazanin Calagar and + Stephen Dean Brown and + Jason Helge Anderson}, + title = {The Effect of Compiler Optimizations on High-Level Synthesis-Generated + Hardware}, + journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, + volume = {8}, + number = {3}, + pages = {14:1--14:26}, + year = {2015}, + url = {https://doi.org/10.1145/2629547}, + doi = {10.1145/2629547}, + timestamp = {Thu, 18 Jun 2020 15:43:43 +0200}, + biburl = {https://dblp.org/rec/journals/trets/HuangLCCXCBA15.bib}, + bibsource = {dblp computer science bibliography, https://dblp.org} +} + +@techreport{pardalos_thesis, +key = {zzzz}, +author = {{Withheld for blind review}}, +title = {Formally verified resource sharing for High +Level Synthesis}, + year = 2021, +}
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