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%add (clk, rst, start, a, b, ret, fin) {
% input clk, rst, start;
% input [31:0] a, b;
% output reg [31:0] ret;
% output reg fin;
%
% reg [31:0] reg_4;
% reg [31:0] reg_3;
\begin{figure}
\begin{lstlisting}
add (x2, x1) {
externctrl { clk -> main.clk }
controllogic {
2: state <= 1;
1: state <= 3;
3: ;
}
datapath {
2: reg_3 <= {{x2 + x1} + 0};
1: fin = 1;
ret = reg_3;
3: fin <= 0;
}
}
\end{lstlisting}
\caption{Example HTL code (part 1)}
\label{fig:example_HTL1}
\end{figure}
\begin{figure}
%main (clk, rst, start, ret, fin) {
% input clk, rst, start;
% output reg [31:0] ret;
% output reg fin;
%
% reg[31:0] reg_1, reg_2, reg_3, reg_4, reg_5, reg_6, reg_7,
% add_0_rst, add_0_a, add_0_b, add_0_ret, add_0_fin,
% add_1_rst, add_1_a, add_1_b, add_1_ret, add_1_fin;
\begin{lstlisting}
main () {
externctrl {
|\HL2{add\_0\_x2 -> add.param[0];}|
|\HL2{add\_0\_x1 -> add.param[1];}|
|\HL2{add\_0\_fin -> add.fin;}|
|\HL2{add\_0\_rst -> add.rst;}|
|\HL2{add\_0\_ret -> add.ret;}|
|\HL3{add\_1\_x2 -> add.param[0];}|
|\HL3{add\_1\_x1 -> add.param[1];}|
|\HL3{add\_1\_fin -> add.fin;}|
|\HL3{add\_1\_rst -> add.rst;}|
|\HL3{add\_1\_ret -> add.ret;}|
|\HL0{clk -> main.clk;}|
}
controllogic {
|\HL1{9: state <= 8;}|
|\HL2{8: state <= 7;}|
|\HL2{7: state <= 12;}|
|\HL2{12: if ({add\_0\_fin == 1}) state <= 6;}|
|\HL2{6: state <= 5;}|
|\HL3{5: state <= 4;}|
|\HL3{4: state <= 10;}|
|\HL3{10: if ({add\_1\_fin == 1}) state <= 3;}|
|\HL3{3: state <= 2;}|
|\HL4{2: state <= 1;}|
|\HL4{1: state <= 11;}|
|\HL0{11: ;}|
}
datapath {
|\HL1{9: reg\_3 <= 0;}|
|\HL2{8: reg\_6 <= 1;}|
|\HL2{7: add\_0\_rst <= 1;}|
|\HL2{add\_0\_a <= reg\_3;}|
|\HL2{add\_0\_b <= reg\_6;}|
|\HL2{12: add\_0\_rst <= 0;}|
|\HL2{reg\_1 <= add\_0\_ret;}|
|\HL2{6: reg\_3 <= reg\_1;}|
|\HL3{5: reg\_5 <= 2;}|
|\HL3{4: add\_1\_rst <= 1;}|
|\HL3{add\_1\_a <= reg\_3;}|
|\HL3{add\_1\_b <= reg\_5;}|
|\HL3{10: add\_1\_rst <= 0;}|
|\HL3{reg\_2 <= add\_1\_ret;}|
|\HL3{3: reg\_3 <= reg\_2;}|
|\HL4{2: reg\_4 <= reg\_3;}|
|\HL4{1: fin = 1;}|
|\HL4{ret = reg\_4;}|
|\HL0{11: fin <= 0;}|
}
}
\end{lstlisting}
\caption{Example HTL code (part 2)}
\label{fig:example_HTL2}
\end{figure}
\appendix
We provide the Verilog output that is generated from our running example (Figures~\ref{fig:example_C} to~\ref{fig:example_HTL}).
\begin{lstlisting}
module main (clk, rst, ret, fin)
input clk, rst;
output reg [31:0] ret;
output reg fin;
reg[31:0] state;
reg[31:0] reg_1, reg_2, reg_3, reg_4, reg_5, reg_6;
reg add_rst, add_fin;
reg[31:0] add_ret, add_x2, add_x1, reg_7, add_state;
always @(posedge clk) // control logic for "add"
if ({add_rst == 1}) begin
add_state <= 2; add_fin <= 0;
end else begin
case (add_state)
|\HL5{2: add\_state <= 1;}|
|\HL5{1: add\_state <= 3;}|
3: ;
default: ;
endcase
end
always @(posedge clk) // datapath for "add"
case (add_state)
|\HL5{2: reg\_7 <= {{add\_x2 + add\_x1} + 0};}|
|\HL5{1: add\_fin = 1;}|
|\HL5{add\_ret = reg\_7;}|
3: add_fin <= 0;
endcase
always @(posedge clk) // control logic for "main"
if ({rst == 1}) begin
state <= 9; fin <= 0;
end else begin
case (state)
|\HL1{9: state <= 8;}|
|\HL2{8: state <= 7;}|
|\HL2{7: state <= 12;}|
|\HL2{12: if ({add\_fin == 1}) state <= 6;}|
|\HL2{6: state <= 5;}|
|\HL3{5: state <= 4;}|
|\HL3{4: state <= 10;}|
|\HL3{10: if ({add\_fin == 1}) state <= 3;}|
|\HL3{3: state <= 2;}|
|\HL4{2: state <= 1;}|
|\HL4{1: state <= 11;}|
|\HL0{11: ;}|
endcase
end
always @(posedge clk) // datapath for "main"
case (state)
|\HL1{9: reg\_3 <= 0;}|
|\HL2{8: reg\_6 <= 1;}|
|\HL2{7: add\_rst <= 1;}|
|\HL2{add\_x2 <= reg\_3;}|
|\HL2{add\_x1 <= reg\_6;}|
|\HL2{12: add\_rst <= 0;}|
|\HL2{reg\_1 <= add\_ret;}|
|\HL2{6: reg\_3 <= reg\_1;}|
|\HL3{5: reg\_5 <= 2;}|
|\HL3{4: add\_rst <= 1;}|
|\HL3{add\_x2 <= reg\_3;}|
|\HL3{add\_x1 <= reg\_5;}|
|\HL3{10: add\_rst <= 0;}|
|\HL3{reg\_2 <= add\_ret;}|
|\HL3{3: reg\_3 <= reg\_2;}|
|\HL4{2: reg\_4 <= reg\_3;}|
|\HL4{1: fin = 1;}|
|\HL4{ret = reg\_4;}|
|\HL0{11: fin <= 0;}|
endcase
endmodule
\end{lstlisting}
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