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author | Yann Herklotz <git@yannherklotz.com> | 2021-10-07 13:43:16 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-10-07 13:43:16 +0100 |
commit | f9ca386bda2fe89287b9bb65d3d28e0c150d8984 (patch) | |
tree | c7ad596237f3d63829d7a7574a93f220a9fc721d /presentation/ExampleRun/output2/fuzz_1/actual_wrong.v | |
download | fpga20_fubfst-f9ca386bda2fe89287b9bb65d3d28e0c150d8984.tar.gz fpga20_fubfst-f9ca386bda2fe89287b9bb65d3d28e0c150d8984.zip |
Diffstat (limited to 'presentation/ExampleRun/output2/fuzz_1/actual_wrong.v')
-rw-r--r-- | presentation/ExampleRun/output2/fuzz_1/actual_wrong.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/presentation/ExampleRun/output2/fuzz_1/actual_wrong.v b/presentation/ExampleRun/output2/fuzz_1/actual_wrong.v new file mode 100644 index 0000000..31508e2 --- /dev/null +++ b/presentation/ExampleRun/output2/fuzz_1/actual_wrong.v @@ -0,0 +1,12 @@ +module top_1(y, clk, wire1); + input clk; + wire [1:0] reg4; + input wire1; + output [1:0] y; + reg reg4_reg[0] = 1'hx; + always @(posedge clk) + reg4_reg[0] <= wire1; + assign reg4[0] = reg4_reg[0] ; + assign reg4[1] = reg4[0]; + assign y = { reg4[0], reg4[0] }; +endmodule |