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author | Yann Herklotz <git@yannherklotz.com> | 2021-10-07 13:43:16 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-10-07 13:43:16 +0100 |
commit | f9ca386bda2fe89287b9bb65d3d28e0c150d8984 (patch) | |
tree | c7ad596237f3d63829d7a7574a93f220a9fc721d /presentation/ExampleRun/output2/fuzz_1/reduce_identity_yosys.v | |
download | fpga20_fubfst-master.tar.gz fpga20_fubfst-master.zip |
Diffstat (limited to 'presentation/ExampleRun/output2/fuzz_1/reduce_identity_yosys.v')
-rw-r--r-- | presentation/ExampleRun/output2/fuzz_1/reduce_identity_yosys.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/presentation/ExampleRun/output2/fuzz_1/reduce_identity_yosys.v b/presentation/ExampleRun/output2/fuzz_1/reduce_identity_yosys.v new file mode 100644 index 0000000..3d5af91 --- /dev/null +++ b/presentation/ExampleRun/output2/fuzz_1/reduce_identity_yosys.v @@ -0,0 +1,9 @@ +module top (y, clk, wire1); + output wire [(32'hb7):(32'h0)] y; + input wire [(1'h0):(1'h0)] clk; + input wire signed [(4'ha):(1'h0)] wire1; + reg signed [(4'he):(1'h0)] reg4 = (1'h0); + assign y = {reg4}; + always + @(posedge clk) reg4 <= wire1; +endmodule |