1 files changed, 12 insertions, 0 deletions
diff --git a/presentation/ExampleRun/output2/fuzz_1/actual_wrong.v b/presentation/ExampleRun/output2/fuzz_1/actual_wrong.v
new file mode 100644
index 0000000..31508e2
--- /dev/null
+++ b/presentation/ExampleRun/output2/fuzz_1/actual_wrong.v
@@ -0,0 +1,12 @@
+module top_1(y, clk, wire1);
+   input clk;
+   wire [1:0] reg4;
+   input wire1;
+   output [1:0] y;
+   reg reg4_reg[0]  = 1'hx;
+   always @(posedge clk)
+     reg4_reg[0]  <= wire1;
+   assign reg4[0] = reg4_reg[0] ;
+   assign reg4[1] = reg4[0];
+   assign y = { reg4[0], reg4[0] };
+endmodule