1 files changed, 52 insertions, 0 deletions
diff --git a/presentation/ExampleRun/output2/fuzz_1/identity/syn_identity_red1.v b/presentation/ExampleRun/output2/fuzz_1/identity/syn_identity_red1.v
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+++ b/presentation/ExampleRun/output2/fuzz_1/identity/syn_identity_red1.v
@@ -0,0 +1,52 @@
+// -*- mode: verilog -*-
+module top #(parameter param30 = (8'hbb)) (y, clk, wire0, wire1, wire2, wire3);
+  output [(32'hb7):(32'h0)] y;
+  input [(1'h0):(1'h0)] clk;
+  input signed [(5'h11):(1'h0)] wire0;
+  input signed [(4'ha):(1'h0)] wire1;
+  input [(4'hd):(1'h0)] wire2;
+  input [(4'h8):(1'h0)] wire3;
+  wire signed [(4'hb):(1'h0)] wire27;
+  wire [(5'h15):(1'h0)] wire26;
+  wire [(5'h10):(1'h0)] wire25;
+  wire [(5'h13):(1'h0)] wire24;
+  reg signed [(4'he):(1'h0)] reg4 = (1'h0);
+  reg [(2'h3):(1'h0)] reg5 = (1'h0);
+  reg [(5'h14):(1'h0)] reg6 = (1'h0);
+  reg signed [(5'h12):(1'h0)] reg7 = (1'h0);
+  reg [(4'hd):(1'h0)] reg8 = (1'h0);
+  wire [(4'hd):(1'h0)] wire9;
+  wire [(4'he):(1'h0)] wire10;
+  assign y = {wire27, wire26, wire25, wire24, reg4, 
+              reg5, reg6, reg7, reg8, wire9, wire10};
+  always
+    @(posedge clk) begin
+      reg4 <=  wire1;
+      if ($unsigned((~&(8'hb2))))
+        begin
+          reg5 <=  reg4;
+          reg6 <=  wire1;
+        end
+      else
+        begin
+          reg5 <=  ($signed(reg7) ? wire2 : reg8[(4'h8):(2'h2)]);
+          reg6 <=  reg6;
+        end
+    end
+  always @* begin
+       reg7 = ((~|((wire0 & {wire3, reg4}) | $unsigned((reg4 != (8'h9d))))) <<< ((wire1[(2'h2):(2'h2)] + ((~(8'ha7)) ?
+                  wire3 : $signed(wire1))) ? $unsigned(((^wire0) + $unsigned(wire3))) : (((reg5 * wire3) ?
+                      wire1 : $unsigned(reg6)) ? {{reg4, wire2}} : (reg5[(1'h0):(1'h0)] ? $signed(reg4) : (~wire3)))));
+       reg8 = (~^$unsigned(reg6));
+  end
+  assign wire9 = (((8'ha2) ?
+                     wire3 : reg8[(4'h9):(4'h8)]) + $signed($signed(wire1)));
+  assign wire10 = $signed($signed($unsigned((~|(wire2 ? wire0 : wire0)))));
+  assign wire24 = $signed((wire1 ?
+                      ((wire1 ? $unsigned(reg5) : ((8'hae) ? reg7 : wire9)) ?
+                          ($unsigned(wire0) && 1'b0) : $unsigned(reg4[(2'h3):(2'h2)])) : $unsigned(wire0)));
+  assign wire25 = $unsigned($signed((~(|reg5))));
+  assign wire26 = reg4[(3'h5):(1'h0)];
+  assign wire27 = {(-wire0[(4'hd):(2'h2)]),
+                      $signed($signed(($signed(reg4) != $unsigned((7'h41)))))};
+endmodule