1 files changed, 27 insertions, 0 deletions
diff --git a/presentation/ExampleRun/output2/fuzz_1/identity/syn_identity_red4.v b/presentation/ExampleRun/output2/fuzz_1/identity/syn_identity_red4.v
new file mode 100644
index 0000000..fd3fd3c
--- /dev/null
+++ b/presentation/ExampleRun/output2/fuzz_1/identity/syn_identity_red4.v
@@ -0,0 +1,27 @@
+// -*- mode: verilog -*-
+module top #(parameter param30 = (8'hbb)) (y, clk, wire0, wire1, wire2, wire3);
+  output [(32'hb7):(32'h0)] y;
+  input [(1'h0):(1'h0)] clk;
+  input signed [(5'h11):(1'h0)] wire0;
+  input signed [(4'ha):(1'h0)] wire1;
+  input [(4'hd):(1'h0)] wire2;
+  input [(4'h8):(1'h0)] wire3;
+  reg signed [(4'he):(1'h0)] reg4 = (1'h0);
+  reg [(2'h3):(1'h0)] reg5 = (1'h0);
+  reg [(5'h14):(1'h0)] reg6 = (1'h0);
+  assign y = {reg4, reg5, reg6};
+  always
+    @(posedge clk) begin
+      reg4 <=  wire1;
+      if ($unsigned((~&(8'hb2))))
+        begin
+          reg5 <=  reg4;
+          reg6 <=  wire1;
+        end
+      else
+        begin
+          reg5 <=  ((1'b0) ? wire2 : (1'b0));
+          reg6 <=  reg6;
+        end
+    end
+endmodule