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module top_1(y, clk, wire1);
input clk;
wire [1:0] reg4;
input wire1;
output [1:0] y;
reg reg4_reg[0] = 1'b0;
always @(posedge clk)
reg4_reg[0] <= wire1;
assign reg4[0] = reg4_reg[0] ;
assign reg4[1] = reg4[0];
assign y = { reg4[0], reg4[0] };
endmodule
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