blob: 81b030dc7135e3ff17d5efe1c1b59ff252494c48 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
// -*- mode: verilog -*-
module top #(parameter param30 = (8'hbb)) (y, clk, wire0, wire1, wire2, wire3);
output [(32'hb7):(32'h0)] y;
input [(1'h0):(1'h0)] clk;
input signed [(5'h11):(1'h0)] wire0;
input signed [(4'ha):(1'h0)] wire1;
input [(4'hd):(1'h0)] wire2;
input [(4'h8):(1'h0)] wire3;
reg signed [(4'he):(1'h0)] reg4 = (1'h0);
reg [(2'h3):(1'h0)] reg5 = (1'h0);
reg [(5'h14):(1'h0)] reg6 = (1'h0);
reg signed [(5'h12):(1'h0)] reg7 = (1'h0);
reg [(4'hd):(1'h0)] reg8 = (1'h0);
assign y = {reg4, reg5, reg6, reg7, reg8};
always
@(posedge clk) begin
reg4 <= wire1;
if ($unsigned((~&(8'hb2))))
begin
reg5 <= reg4;
reg6 <= wire1;
end
else
begin
reg5 <= ($signed(reg7) ? wire2 : reg8[(4'h8):(2'h2)]);
reg6 <= reg6;
end
end
always @* begin
reg7 = ((~|((wire0 & {wire3, reg4}) | $unsigned((reg4 != (8'h9d))))) <<< ((wire1[(2'h2):(2'h2)] + ((~(8'ha7)) ?
wire3 : $signed(wire1))) ? $unsigned(((^wire0) + $unsigned(wire3))) : (((reg5 * wire3) ?
wire1 : $unsigned(reg6)) ? {{reg4, wire2}} : (reg5[(1'h0):(1'h0)] ? $signed(reg4) : (~wire3)))));
reg8 = (~^$unsigned(reg6));
end
endmodule
|
