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// -*- mode: verilog -*-
module top #(parameter param30 = (8'hbb)) (y, clk, wire0, wire1, wire2, wire3);
output [(32'hb7):(32'h0)] y;
input [(1'h0):(1'h0)] clk;
input signed [(5'h11):(1'h0)] wire0;
input signed [(4'ha):(1'h0)] wire1;
input [(4'hd):(1'h0)] wire2;
input [(4'h8):(1'h0)] wire3;
reg signed [(4'he):(1'h0)] reg4 = (1'h0);
assign y = {reg4};
always
@(posedge clk) begin
reg4 <= wire1;
end
endmodule
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