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author | Yann Herklotz <git@yannherklotz.com> | 2021-02-24 12:54:19 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-02-24 12:54:19 +0000 |
commit | 88ae1f4919e337903db03359682913483c287bda (patch) | |
tree | 9f495122f7c34b4516db46853499605c5a13809d | |
parent | 95f15280705a5aee5215666675f666d35f5f43f4 (diff) | |
download | latte21_hlstpc-88ae1f4919e337903db03359682913483c287bda.tar.gz latte21_hlstpc-88ae1f4919e337903db03359682913483c287bda.zip |
Fix the citation
-rw-r--r-- | main.tex | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -185,7 +185,7 @@ \renewcommand{\epigraphsize}{\normalsize} \renewcommand{\epigraphflush}{center} \renewcommand{\epigraphrule}{0pt} -\epigraph{\textit{High-level synthesis research and development is inherently prone to introducing bugs or regressions in the final circuit functionality.}}{--- Andrew Canis \JW{Co-founder of LegUp Computing}~\cite{canis15_legup}} +\epigraph{\textit{High-level synthesis research and development is inherently prone to introducing bugs or regressions in the final circuit functionality.}}{--- Andrew Canis~\cite{canis15_legup}\\Co-founder of LegUp Computing} %\JW{Nice quote; I'd be tempted to tinker with whether it can be formatted a bit more elegantly, like at https://style.mla.org/styling-epigraphs/} Research in high-level synthesis (HLS) often concentrates on performance, trying to achieve the lowest area with the shortest run-time. What is often overlooked is ensuring that the high-level synthesis tool is indeed correct, which means that it outputs a correct hardware design. Instead, the design is often meticulously tested, often using the higher level design as a model. As these tests are performed on the hardware design directly, they have to be run on a simulator, which takes much longer than if the original C was tested. Any formal properties obtained from the C code would also have to be checked again in the resulting design, to ensure that these hold there as well, as the synthesis tool may have translated the input incorrectly. |