Fix diagram

1 files changed, 17 insertions, 12 deletions

diff --git a/algorithm.tex b/algorithm.tex
index b19cac6..ee7de53 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -8,26 +8,31 @@ This section covers the main architecture of the HLS tool, and the way in which
   \centering
   \resizebox{0.47\textwidth}{!}{
   \begin{tikzpicture}
-    [language/.style={fill=white,rounded corners=2pt}]
+    [language/.style={fill=white,rounded corners=3pt,minimum height=7mm},
+    continuation/.style={}]
     \fill[compcert,rounded corners=3pt] (-1,-1) rectangle (9,1.5);
     \fill[formalhls,rounded corners=3pt] (-1,-1.5) rectangle (9,-2.5);
-    \node[language] at (0,0) (clight) {Clight};
-    \node[language] at (2,0) (cminor) {C\#minor};
-    \node[language] at (4,0) (rtl) {3AC};
-    \node[language] at (6,0) (ltl) {LTL};
-    \node[language] at (8,0) (ppc) {PPC};
-    \node[language] at (4,-2) (dfgstmd) {HTL};
-    \node[language] at (7,-2) (verilog) {Verilog};
+    \node[language] at (-0.3,0) (clight) {Clight};
+    \node[continuation] at (1,0) (conta) {$\cdots$};
+    \node[language] at (2.7,0) (cminor) {CminorSel};
+    \node[language] at (4.7,0) (rtl) {3AC};
+    \node[language] at (6.2,0) (ltl) {LTL};
+    \node[language] at (8.4,0) (ppc) {PPC};
+    \node[continuation] at (7.3,0) (contb) {$\cdots$};
+    \node[language] at (4.7,-2) (dfgstmd) {HTL};
+    \node[language] at (6.7,-2) (verilog) {Verilog};
     \node at (0,1) {\compcert{}};
     \node at (0,-2) {Vericert};
-    \draw[->] (clight) -- (cminor);
-    \draw[->,dashed] (cminor) -- (rtl);
+    \draw[->] (clight) -- (conta);
+    \draw[->] (conta) -- (cminor);
+    \draw[->] (cminor) -- (rtl);
     \draw[->] (rtl) -- (ltl);
-    \draw[->,dashed] (ltl) -- (ppc);
+    \draw[->] (ltl) -- (contb);
+    \draw[->] (contb) -- (ppc)
     \draw[->] (rtl) -- (dfgstmd);
     \draw[->] (dfgstmd) -- (verilog);
   \end{tikzpicture}}
-  \caption{Verilog back end to Compcert, branching off at the three address code (3AC), at which point the three address code is transformed into a state machine.  Finally, it is transformed to a hardware description of the state machine in Verilog. \JW{The dashed arrows look like `optional' arrows to my mind. To suggest a sequence of arrows (which is what you intend) I would draw something more like `-->...-->'.}}%
+  \caption{Verilog back end to Compcert, branching off at the three address code (3AC), at which point the three address code is transformed into a state machine.  Finally, it is transformed to a hardware description of the state machine in Verilog.}%
   \label{fig:rtlbranch}
 \end{figure}