Update references

2 files changed, 31 insertions, 27 deletions

diff --git a/references.bib b/references.bib
index 9c18163..78a317a 100644
--- a/references.bib
+++ b/references.bib
@@ -335,19 +335,6 @@
   year = {2008},
 }
 
-@article{06_ieee_stand_veril_hardw_descr_languag,
-  author          = {},
-  title           = {IEEE Standard for Verilog Hardware Description Language},
-  journal         = {IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
-  volume          = {},
-  number          = {},
-  pages           = {1-590},
-  year            = {2006},
-  doi             = {10.1109/IEEESTD.2006.99495},
-  ISSN            = {},
-  month           = {April},
-}
-
 @inproceedings{loow19_verif_compil_verif_proces,
   author =       {L\"{o}\"{o}w, Andreas and Kumar, Ramana and Tan, Yong Kiam and
                   Myreen, Magnus O. and Norrish, Michael and Abrahamsson, Oskar
@@ -418,17 +405,34 @@
   isbn            = 0070163332,
 }
 
-@techreport{05_veril_regis_trans_level_synth,
-  type =         {Standard},
-  key =          {IEEE Std 1364.1},
-  title =        {{IEEE} Standard for {Verilog} Register Transfer Level Synthesis},
-  journal =      {IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1},
-  volume =       {},
-  number =       {},
-  pages =        {1-116},
-  year =         {2005},
-  doi =          {10.1109/IEEESTD.2005.339572},
-  ISSN =         {},
-  keywords =     {IEC Standards;Verilog;Registers},
-  month =        {},
+@article{05_ieee_stand_veril_regis_trans_level_synth,
+  title           = {{IEEE} Standard for {Verilog} Register Transfer Level Synthesis},
+  journal         = {IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1},
+  volume          = {},
+  number          = {},
+  pages           = {1-116},
+  year            = {2005},
+  doi             = {10.1109/IEEESTD.2005.339572},
+  url             = {https://doi.org/10.1109/IEEESTD.2005.339572},
+  ISSN            = {},
+  key             = {IEEE Std 1364.1},
+  keywords        = {IEC Standards;Verilog;Registers},
+  month           = {},
+  type            = {Standard},
+}
+
+@article{06_ieee_stand_veril_hardw_descr_languag,
+  author          = {},
+  title           = {{IEEE} Standard for Verilog Hardware Description Language},
+  journal         = {IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
+  volume          = {},
+  number          = {},
+  pages           = {1-590},
+  year            = {2006},
+  doi             = {10.1109/IEEESTD.2006.99495},
+  url             = {https://doi.org/10.1109/IEEESTD.2006.99495},
+  ISSN            = {},
+  key             = {IEEE Std 1364},
+  month           = {April},
+  type            = {Standard},
 }
diff --git a/verilog.tex b/verilog.tex
index 0e728c0..27c93fc 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -2,7 +2,7 @@
 
 This section describes the Verilog semantics that were chosen for the target language, including the changes that were made to the semantics to be a better fit as an HLS target.
 
-Verilog is a hardware description language commonly used to design hardware.  A Verilog design can then be synthesised into logic gates which describes how different gates connect to each other, called a netlist.  This representation can then be mapped onto either a field-programmable gate array (FPGA) or turned into an application-specific integrated circuit (ASIC) to implement the design that was described in Verilog.  The Verilog standard is quite large though, and not all Verilog features are needed to be able to describe hardware.  Many Verilog features are only useful for simulation and do not affect the actual hardware itself, we can therefore restrict the Verilog semantics to the synthesisable subset of Verilog~\cite{05_veril_regis_trans_level_synth}.  In addition to that, HLS dictates which Verilog constructs are generated, meaning the Verilog subset that has to be modelled by the semantics can be reduced even further to only support the constructs that are needed.  Supporting a smaller subset in the semantics also means that there is less chance that the standard is misunderstood, and that the semantics actually model how the Verilog is simulated and synthesised by existing tools and how it is dictated by the standard.
+Verilog~\cite{06_ieee_stand_veril_hardw_descr_languag} is a hardware description language commonly used to design hardware.  A Verilog design can then be synthesised into logic gates which describes how different gates connect to each other, called a netlist.  This representation can then be mapped onto either a field-programmable gate array (FPGA) or turned into an application-specific integrated circuit (ASIC) to implement the design that was described in Verilog.  The Verilog standard is quite large though, and not all Verilog features are needed to be able to describe hardware.  Many Verilog features are only useful for simulation and do not affect the actual hardware itself, we can therefore restrict the Verilog semantics to the synthesisable subset of Verilog~\cite{05_ieee_stand_veril_regis_trans_level_synth}.  In addition to that, HLS dictates which Verilog constructs are generated, meaning the Verilog subset that has to be modelled by the semantics can be reduced even further to only support the constructs that are needed.  Supporting a smaller subset in the semantics also means that there is less chance that the standard is misunderstood, and that the semantics actually model how the Verilog is simulated and synthesised by existing tools and how it is dictated by the standard.
 %~\NR{Didn't get this sentence? Do you mean that the HLS algo further restricts the synthesisable subset?}\YH{Yes basically, because we get to choose what we generate.  For example, we don't have to support combinational always blocks.}
 %\NR{What is the distinction here between the semantics and simulation? Discuss.}\YH{Tried to clarify that I meant simulation and synthesis by tools and how it should be understood from the standard}