Fix algorithm section

1 files changed, 2 insertions, 3 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 5bde1a5..5ed47ad 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -243,12 +243,11 @@ Figure~\ref{fig:accumulator_diagram} shows the resulting FSMD architecture. The
 
 %\JP{Does it? Verilog has neither physical registers nor RAMs, just language constructs which the synthesiser might implement with registers and RAMs. We should be clear whether we're talking about the HDL representation, or the synthesised result: in our case these can be very different since we don't target any specific architectural features of an FPGA fabric of ASIC process.}
 \paragraph{Translating memory}
-\YH{Need to add information to this.}
-Typically, HLS-generated hardware consists of a sea of registers and RAM memories. 
+Typically, HLS-generated hardware consists of a sea of registers and RAM memories.
 This memory view is very different to the C memory model, so we perform the following translation. 
 Variables that do not have their address taken are kept in registers, which correspond to the registers in 3AC.
 All address-taken variables, arrays, and structs are kept in RAM.
-The stack of the main function becomes an unpacked array of 32-bit integers, which may be translated to a RAM when the hardware description is passed through a synthesis tool. 
+The stack of the main function becomes an unpacked array of 32-bit integers, which is translated to a RAM when the hardware description is passed through a synthesis tool.  We generate a well-formed RAM template to ensure that a RAM is present in the final hardware, performing reads and writes using the signals that the RAM template exposes.
 Finally, global variables are not translated in \vericert{} at the moment.
 A high-level overview of the architecture can be seen in Figure~\ref{fig:accumulator_diagram}.