Work on Nadesh's comments in Verilog section

3 files changed, 18 insertions, 3 deletions

diff --git a/data/accumulator.c b/data/accumulator.c
index 007ae2b..aa7171a 100644
--- a/data/accumulator.c
+++ b/data/accumulator.c
@@ -1,9 +1,9 @@
 int main() {
     int x[3] = {1, 2, 3};
-    int sum = 0, incr = 1;
+    int sum = 0;
     for (int i = 0;
          i < 3;
-         i=i+incr)
+         i++)
         sum += x[i];
     return sum;
 }
diff --git a/references.bib b/references.bib
index ee57c3b..9c18163 100644
--- a/references.bib
+++ b/references.bib
@@ -417,3 +417,18 @@
   edition         = {1st},
   isbn            = 0070163332,
 }
+
+@techreport{05_veril_regis_trans_level_synth,
+  type =         {Standard},
+  key =          {IEEE Std 1364.1},
+  title =        {{IEEE} Standard for {Verilog} Register Transfer Level Synthesis},
+  journal =      {IEC 62142-2005 First edition 2005-06 IEEE Std 1364.1},
+  volume =       {},
+  number =       {},
+  pages =        {1-116},
+  year =         {2005},
+  doi =          {10.1109/IEEESTD.2005.339572},
+  ISSN =         {},
+  keywords =     {IEC Standards;Verilog;Registers},
+  month =        {},
+}
diff --git a/verilog.tex b/verilog.tex
index d9bcae2..b4b2d08 100644
--- a/verilog.tex
+++ b/verilog.tex
@@ -1,6 +1,6 @@
 \section{Verilog}
 
-Verilog is a hardware description language commonly used to design hardware.  A Verilog design can then be synthesised into more basic logic~\NR{Did you mean logic gate?} which describes how different gates connect to each other, called a netlist.  This representation can then be put~\NR{mapped?} onto either a field-programmable gate array (FPGA) or turned into an application-specific integrated circuit (ASIC) to implement the design that was described in Verilog.  The Verilog standard is quite large though, and not all Verilog features are needed to be able to describe hardware.~\NR{Will be good to use the word synthesisable subset somewhere in this discussion.} Many Verilog features are only useful for simulation and do not affect the actual hardware itself, which means that these features do not have to be modelled in the semantics.  In addition to that, as the HLS algorithm dictates which Verilog constructs are generated, meaning the Verilog subset that has to be modelled by the semantics can be reduced even further to only support the constructs that are needed.~\NR{Didn't get this sentence? Do you mean that the HLS algo further restricts the synthesisable subset?}  Only supporting a smaller subset in the semantics also means that there is less chance that the standard is misunderstood, and that the semantics actually model how the Verilog is simulated.
+Verilog is a hardware description language commonly used to design hardware.  A Verilog design can then be synthesised into logic gates which describes how different gates connect to each other, called a netlist.  This representation can then be mapped onto either a field-programmable gate array (FPGA) or turned into an application-specific integrated circuit (ASIC) to implement the design that was described in Verilog.  The Verilog standard is quite large though, and not all Verilog features are needed to be able to describe hardware.  Many Verilog features are only useful for simulation and do not affect the actual hardware itself, we can therefore restrict the Verilog semantics to the synthesisable subset of Verilog~\cite{05_veril_regis_trans_level_synth}.  In addition to that, as the HLS algorithm dictates which Verilog constructs are generated, meaning the Verilog subset that has to be modelled by the semantics can be reduced even further to only support the constructs that are needed.~\NR{Didn't get this sentence? Do you mean that the HLS algo further restricts the synthesisable subset?}\YH{Yes basically, because we get to choose what we generate.  For example, we don't have to support combinational always blocks.}  Only supporting a smaller subset in the semantics also means that there is less chance that the standard is misunderstood, and that the semantics actually model how the Verilog is simulated.
 \NR{What is the distinction here between the semantics and simulation? Discuss.}
 
 The Verilog semantics are based on the semantics proposed by \citet{loow19_verif_compil_verif_proces}, which were used to create a formal translation from HOL logic into a Verilog circuit.  These semantics are quite practical as they restrict themselves to a small subset of Verilog, which can nonetheless be used to model all hardware constructs one would want to design. An abstraction of the Verilog syntax that is generated is shown below: