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| author | Yann Herklotz <git@yannherklotz.com> | 2021-09-09 21:00:41 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-09 21:00:41 +0100 |
| commit | 6f7b7f66f0b420a318aa5c3287cbd7c8250d3dd1 (patch) | |
| tree | 349be76159a425d9bad14ed5d18028c1f72c44c8 | |
| parent | f4d791dbd4fdb4985c017c58c45ca583626a484a (diff) | |
| download | oopsla21_fvhls-6f7b7f66f0b420a318aa5c3287cbd7c8250d3dd1.tar.gz oopsla21_fvhls-6f7b7f66f0b420a318aa5c3287cbd7c8250d3dd1.zip | |
Fix some more titles
| -rw-r--r-- | algorithm.tex | 2 | ||||
| -rw-r--r-- | limitations.tex | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/algorithm.tex b/algorithm.tex index 81763d7..1783c29 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -223,7 +223,7 @@ endmodule % \NR{Is the default in line 41 of (c) supposed to be empty?}\YH{Yep, that's how it's generated.} \end{figure} -\subsection{Translating C to Verilog, by Example} +\subsection{Translating C to Verilog by Example} Figure~\ref{fig:accumulator_c_rtl} illustrates the translation of a simple program that stores and retrieves values from an array. In this section, we describe the stages of the \vericert{} translation, referring to this program as an example. diff --git a/limitations.tex b/limitations.tex index 141ee91..a470028 100644 --- a/limitations.tex +++ b/limitations.tex @@ -32,7 +32,7 @@ The introduction of pipelined operators to \vericert{}, especially for division, %JW I've chopped the following sentence because it felt like it was going into too much detail. %However, 3ACPar would have to be modified to also describe such instructions so that these can be placed optimally using the external scheduling algorithm. -\subsection{Limitations on the software input} +\subsection{Limitations on the Software Input} %This section describes the limitations and possible improvements to the software input accepted by \vericert{}. |