Transform diagram into a Moore machine

1 files changed, 9 insertions, 9 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 1a2d191..3d65607 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -115,25 +115,25 @@ endmodule
   \begin{subfigure}{0.45\linewidth}
     \centering
     \begin{tikzpicture}
-      \node[draw,circle,inner sep=6pt] (s0) at (0,0) {$S_{\mathit{start}}$};
-      \node[draw,circle,inner sep=8pt] (s1) at (1.5,-3) {$S_{0}$};
-      \node[draw,circle,inner sep=8pt] (s2) at (3,0) {$S_{1}$};
-      \node (s2s) at ($(s2.west) + (-0.3,1)$) {\texttt{x0/1}};
-      \node (s2ss) at ($(s2.east) + (0.3,1)$) {\texttt{1x/1}};
+      \node[draw,circle,inner sep=6pt] (s0) at (0,0) {$S_{\mathit{start}} / \texttt{x}$};
+      \node[draw,circle,inner sep=8pt] (s1) at (1.5,-3) {$S_{0} / \texttt{1}$};
+      \node[draw,circle,inner sep=8pt] (s2) at (3,0) {$S_{1} / \texttt{1}$};
+      \node (s2s) at ($(s2.west) + (-0.3,1)$) {\texttt{x0}};
+      \node (s2ss) at ($(s2.east) + (0.3,1)$) {\texttt{1x}};
       \draw[-{Latex[length=2mm,width=1.4mm]}] ($(s0.west) + (-0.3,1)$) to [out=0,in=120] (s0);
       \draw[-{Latex[length=2mm,width=1.4mm]}] (s0)
-           to [out=-90,in=150] node[midway,left] {\texttt{01/x}} (s1);
+           to [out=-90,in=150] node[midway,left] {\texttt{01}} (s1);
       \draw[-{Latex[length=2mm,width=1.4mm]}] (s1)
-      to [out=80,in=220] node[midway,left] {\texttt{xx/1}} (s2);
+      to [out=80,in=220] node[midway,left] {\texttt{xx}} (s2);
       \draw[-{Latex[length=2mm,width=1.4mm]}] (s2)
-      to [out=260,in=50] node[midway,right] {\texttt{01/1}} (s1);
+      to [out=260,in=50] node[midway,right] {\texttt{01}} (s1);
       \draw[-{Latex[length=2mm,width=1.4mm]}] (s2)
       to [out=120,in=40] ($(s2.west) + (-0.3,0.7)$) to [out=220,in=170] (s2);
       \draw[-{Latex[length=2mm,width=1.4mm]}] (s2)
       to [out=60,in=130] ($(s2.east) + (0.3,0.7)$) to [out=310,in=10] (s2);
     \end{tikzpicture}
   \end{subfigure}
-  \caption{A simple state machine implemented in Verilog, with its diagrammatic representation on the right. The x's stand for don't cares and each transition is labelled with the values of the inputs \texttt{rst} and \texttt{y} and output \texttt{z}.}%
+  \caption{A simple state machine implemented in Verilog, with its diagrammatic representation on the right. The x's stand for don't cares and each transition is labelled with the values of the inputs \texttt{rst} and \texttt{y} that trigger the transition.  The output that will be produced is shown in each state.}%
   \label{fig:tutorial:state_machine}
 \end{figure}