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authorYann Herklotz <git@yannherklotz.com>2020-11-12 12:33:12 +0000
committerYann Herklotz <git@yannherklotz.com>2020-11-12 12:33:12 +0000
commitc6fcc3d366c9a39fce73c1e5d20b7c0bdf515c86 (patch)
tree8d11e4abbea925f1093c491b0753a0f062de2058
parentfc18d96bbfb066d3b33c3e61706f7cf03159fc93 (diff)
downloadoopsla21_fvhls-c6fcc3d366c9a39fce73c1e5d20b7c0bdf515c86.tar.gz
oopsla21_fvhls-c6fcc3d366c9a39fce73c1e5d20b7c0bdf515c86.zip
Add coq mechanisation
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The \compcert{} semantics for the \texttt{Oshrximm} instruction express it's operation exactly as shown in the equation above, even though in hardware the computation that would be performed would be different. In \vericert{}, if the same operation would be implemented using Verilog operators, it is not guaranteed to be optimised correctly by the synthesis tools that convert the Verilog into a circuit. To guarantee an output that does not include divides, we therefore have to express it in Verilog using shifts, and then prove that this representation is equivalent to the divide representation used in the \compcert{} semantics. This proof discovered quite a few bugs in our initial implementation of optimisations, which rounded to $-\infty$ instead of 0.
+\subsection{Coq Mechanisation}
+
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