Remove scalebox

1 files changed, 43 insertions, 42 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 930ce00..5138915 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -262,15 +262,15 @@ Compared to plain Verilog, HTL is simpler to manipulate and analyse, thereby mak
   \centering
 \definecolor{control}{HTML}{b3e2cd}
 \definecolor{data}{HTML}{fdcdac}
-\scalebox{1.2}{%
 \begin{tikzpicture}
+  \begin{scope}[scale=1.15]
   \fill[control,fill opacity=1] (6.5,0) rectangle (12,5);
   \fill[data,fill opacity=1] (0,0) rectangle (5.5,5);
-  \node at (1,4.7) {\footnotesize Data-path};
-  \node at (7.5,4.7) {\footnotesize Control Logic};
+  \node at (1,4.7) {Data-path};
+  \node at (7.5,4.7) {Control Logic};
 
   \fill[white,rounded corners=10pt] (7,0.5) rectangle (11.5,2.2);
-  \node at (8,2) {\tiny Next State FSM};
+  \node at (8,2) {\footnotesize Next State FSM};
   \foreach \x in {8,...,2}
     {\pgfmathtruncatemacro{\y}{8-\x}%
       \node[draw,circle,inner sep=0,minimum size=10,scale=0.8] (s\x) at (7.5+\y/2,1.35) {\tiny \x};}
@@ -287,34 +287,34 @@ Compared to plain Verilog, HTL is simpler to manipulate and analyse, thereby mak
   \draw[-{Latex[length=1mm,width=0.7mm]}] let \p1 = (nextstate) in
     (11.5,1.25) -| (11.75,\y1) -- (nextstate);
   \draw let \p1 = (nextstate) in (nextstate) -- (6,\y1) |- (6,1.5);
-  \node[scale=0.4,rotate=60] at (7.5,0.75) {\texttt{clk}};
-  \node[scale=0.4,rotate=60] at (7.7,0.75) {\texttt{rst}};
+  \node[scale=0.5,rotate=60] at (7.5,0.75) {\texttt{clk}};
+  \node[scale=0.5,rotate=60] at (7.7,0.75) {\texttt{rst}};
   \draw[-{Latex[length=1mm,width=0.7mm]}] (7.65,-0.5) -- (7.65,0.5);
   \draw[-{Latex[length=1mm,width=0.7mm]}] (7.45,-0.5) -- (7.45,0.5);
 
   \fill[white,rounded corners=10pt] (2,0.5) rectangle (5,3);
   \filldraw[fill=white] (0.25,0.5) rectangle (1.5,2.75);
-  \node at (2.6,2.8) {\tiny Update};
-  \node[align=center] at (0.875,2.4) {\tiny \texttt{RAM}};
-  \node[scale=0.4] at (4.7,1.5) {\texttt{state}};
+  \node at (2.6,2.8) {\footnotesize Update};
+  \node[align=center] at (0.875,2.55) {\footnotesize \texttt{RAM}};
+  \node[scale=0.5] at (4.7,1.5) {\texttt{state}};
   \draw[-{Latex[length=1mm,width=0.7mm]}] (6,1.5) -- (5,1.5);
   \draw[-{Latex[length=1mm,width=0.7mm]}] (6,1.5) -- (7,1.5);
-  \node[scale=0.4,rotate=60] at (4.1,0.9) {\texttt{finished}};
-  \node[scale=0.4,rotate=60] at (3.9,0.95) {\texttt{return\_val}};
-  \node[scale=0.4,rotate=60] at (2.5,0.75) {\texttt{clk}};
-  \node[scale=0.4,rotate=60] at (2.7,0.75) {\texttt{rst}};
-
-  \node[scale=0.4,right,inner sep=5pt] (ram1) at (2,2.1) {\texttt{u\_en}};
-  \node[scale=0.4,right,inner sep=5pt] (ram2) at (2,1.9) {\texttt{wr\_en}};
-  \node[scale=0.4,right,inner sep=5pt] (ram3) at (2,1.7) {\texttt{addr}};
-  \node[scale=0.4,right,inner sep=5pt] (ram4) at (2,1.5) {\texttt{d\_in}};
-  \node[scale=0.4,right,inner sep=5pt] (ram5) at (2,1.3) {\texttt{d\_out}};
-
-  \node[scale=0.4,left,inner sep=5pt] (r1) at (1.5,2.1) {\texttt{u\_en}};
-  \node[scale=0.4,left,inner sep=5pt] (r2) at (1.5,1.9) {\texttt{wr\_en}};
-  \node[scale=0.4,left,inner sep=5pt] (r3) at (1.5,1.7) {\texttt{addr}};
-  \node[scale=0.4,left,inner sep=5pt] (r4) at (1.5,1.5) {\texttt{d\_in}};
-  \node[scale=0.4,left,inner sep=5pt] (r5) at (1.5,1.3) {\texttt{d\_out}};
+  \node[scale=0.5,rotate=60] at (4.1,0.9) {\texttt{finished}};
+  \node[scale=0.5,rotate=60] at (3.9,0.95) {\texttt{return\_val}};
+  \node[scale=0.5,rotate=60] at (2.5,0.75) {\texttt{clk}};
+  \node[scale=0.5,rotate=60] at (2.7,0.75) {\texttt{rst}};
+
+  \node[scale=0.5,right,inner sep=5pt] (ram1) at (2,2.1) {\texttt{u\_en}};
+  \node[scale=0.5,right,inner sep=5pt] (ram2) at (2,1.9) {\texttt{wr\_en}};
+  \node[scale=0.5,right,inner sep=5pt] (ram3) at (2,1.7) {\texttt{addr}};
+  \node[scale=0.5,right,inner sep=5pt] (ram4) at (2,1.5) {\texttt{d\_in}};
+  \node[scale=0.5,right,inner sep=5pt] (ram5) at (2,1.3) {\texttt{d\_out}};
+
+  \node[scale=0.5,left,inner sep=5pt] (r1) at (1.5,2.1) {\texttt{u\_en}};
+  \node[scale=0.5,left,inner sep=5pt] (r2) at (1.5,1.9) {\texttt{wr\_en}};
+  \node[scale=0.5,left,inner sep=5pt] (r3) at (1.5,1.7) {\texttt{addr}};
+  \node[scale=0.5,left,inner sep=5pt] (r4) at (1.5,1.5) {\texttt{d\_in}};
+  \node[scale=0.5,left,inner sep=5pt] (r5) at (1.5,1.3) {\texttt{d\_out}};
 
   \draw[-{Latex[length=1mm,width=0.7mm]}] (ram1) -- (r1);
   \draw[-{Latex[length=1mm,width=0.7mm]}] (ram2) -- (r2);
@@ -330,17 +330,17 @@ Compared to plain Verilog, HTL is simpler to manipulate and analyse, thereby mak
   \foreach \x in {0,...,1}
   {\draw (0.25,1-0.25*\x) -- (1.5,1-0.25*\x); \node at (0.875,0.88-0.25*\x) {\tiny \x};}
 
-  %\node[scale=0.4] at (1.2,2.2) {\texttt{wr\_en}};
-  %\node[scale=0.4] at (1.2,2) {\texttt{wr\_addr}};
-  %\node[scale=0.4] at (1.2,1.8) {\texttt{wr\_data}};
-  %\node[scale=0.4] at (1.2,1.4) {\texttt{r\_addr}};
-  %\node[scale=0.4] at (1.2,1.2) {\texttt{r\_data}};
+  %\node[scale=0.5] at (1.2,2.2) {\texttt{wr\_en}};
+  %\node[scale=0.5] at (1.2,2) {\texttt{wr\_addr}};
+  %\node[scale=0.5] at (1.2,1.8) {\texttt{wr\_data}};
+  %\node[scale=0.5] at (1.2,1.4) {\texttt{r\_addr}};
+  %\node[scale=0.5] at (1.2,1.2) {\texttt{r\_data}};
   %
-  %\node[scale=0.4] at (2.3,2.2) {\texttt{wr\_en}};
-  %\node[scale=0.4] at (2.3,2) {\texttt{wr\_addr}};
-  %\node[scale=0.4] at (2.3,1.8) {\texttt{wr\_data}};
-  %\node[scale=0.4] at (2.3,1.4) {\texttt{r\_addr}};
-  %\node[scale=0.4] at (2.3,1.2) {\texttt{r\_data}};
+  %\node[scale=0.5] at (2.3,2.2) {\texttt{wr\_en}};
+  %\node[scale=0.5] at (2.3,2) {\texttt{wr\_addr}};
+  %\node[scale=0.5] at (2.3,1.8) {\texttt{wr\_data}};
+  %\node[scale=0.5] at (2.3,1.4) {\texttt{r\_addr}};
+  %\node[scale=0.5] at (2.3,1.2) {\texttt{r\_data}};
   %
   %\draw[-{Latex[length=1mm,width=0.7mm]}] (2,2.2) -- (1.5,2.2);
   %\draw[-{Latex[length=1mm,width=0.7mm]}] (2,2) -- (1.5,2);
@@ -349,17 +349,18 @@ Compared to plain Verilog, HTL is simpler to manipulate and analyse, thereby mak
   %\draw[-{Latex[length=1mm,width=0.7mm]}] (1.5,1.2) -- (2,1.2);
 
   \filldraw[fill=white] (2.8,3.25) rectangle (4.2,4.75);
-  \node at (3.5,4.55) {\tiny \texttt{Registers}};
+  \node at (3.5,4.55) {\footnotesize \texttt{Registers}};
   \draw[-{Latex[length=1mm,width=0.7mm]}] (2,2.4) -| (1.75,4) -- (2.8,4);
   \draw[-{Latex[length=1mm,width=0.7mm]}] (4.2,4) -- (5.25,4) |- (5,2.4);
   \draw[-{Latex[length=1mm,width=0.7mm]}] (5.25,2.4) -- (6.2,2.4) |- (7,1.8);
 
-  \node[scale=0.4] at (3.5,4.2) {\texttt{reg\_1}};
-  \node[scale=0.4] at (3.5,4) {\texttt{reg\_2}};
-  \node[scale=0.4] at (3.5,3.8) {\texttt{reg\_3}};
-  \node[scale=0.4] at (3.5,3.6) {\texttt{reg\_4}};
-  \node[scale=0.4] at (3.5,3.4) {\texttt{reg\_5}};
-\end{tikzpicture}}
+  \node[scale=0.5] at (3.5,4.2) {\texttt{reg\_1}};
+  \node[scale=0.5] at (3.5,4) {\texttt{reg\_2}};
+  \node[scale=0.5] at (3.5,3.8) {\texttt{reg\_3}};
+  \node[scale=0.5] at (3.5,3.6) {\texttt{reg\_4}};
+  \node[scale=0.5] at (3.5,3.4) {\texttt{reg\_5}};
+\end{scope}
+\end{tikzpicture}
   \Description{Diagram displaying the data-path and its internal modules, as well as the control logic and its state machine.}
   \caption{The FSMD for the example shown in Fig.~\ref{fig:accumulator_c_rtl}, split into a data-path and control logic for the next state calculation.  The Update block takes the current state, current values of all registers and at most one value stored in the RAM, and calculates a new value that can either be stored back in the  or in a register.}\label{fig:accumulator_diagram}
 \end{figure*}