Modify the diagram

1 files changed, 11 insertions, 6 deletions

diff --git a/algorithm.tex b/algorithm.tex
index cf2eb50..71add1f 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -34,18 +34,20 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
   \begin{tikzpicture}
     [language/.style={fill=white,rounded corners=3pt,minimum height=7mm},
     continuation/.style={}]
-    \fill[compcert,rounded corners=3pt] (-1,-0.5) rectangle (9,1.5);
-    \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9,-2);
+    \fill[compcert,rounded corners=3pt] (-1,-0.5) rectangle (10,2);
+    \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (10,-2);
     \node[language] at (-0.3,0) (clight) {Clight};
     \node[continuation] at (1,0) (conta) {$\cdots$};
     \node[language] at (2.7,0) (cminor) {CminorSel};
     \node[language] at (4.7,0) (rtl) {3AC};
     \node[language] at (6.2,0) (ltl) {LTL};
-    \node[language] at (8.4,0) (ppc) {PPC};
+    \node[language,anchor=west] at (8.4,0) (aarch) {aarch64};
+    \node[language,anchor=west] at (8.4,0.8) (x86) {x86};
+    \node[continuation,anchor=west] at (8.4,1.4) (backs) {$\cdots$};
     \node[continuation] at (7.3,0) (contb) {$\cdots$};
     \node[language] at (4.7,-1.5) (htl) {HTL};
     \node[language] at (6.7,-1.5) (verilog) {Verilog};
-    \node at (0,1) {\bf\compcert{}};
+    \node at (0,1.5) {\bf\compcert{}};
     \node at (0,-1.5) {\bf\vericert{}};
     \node[align=center] at (3.5,-2.4) {\footnotesize RAM\\[-0.5em]\footnotesize insertion};
     \draw[->,thick] (clight) -- (conta);
@@ -53,12 +55,15 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
     \draw[->,thick] (cminor) -- (rtl);
     \draw[->,thick] (rtl) -- (ltl);
     \draw[->,thick] (ltl) -- (contb);
-    \draw[->,thick] (contb) -- (ppc);
+    \draw[->,thick] (contb) -- (aarch);
+    \draw[->,thick] (contb) to [out=0,in=210] (x86);
+    \draw[->,thick] (contb) to [out=0,in=200] (backs);
     \draw[->,thick] (rtl) -- (htl);
     \draw[->,thick] (htl) -- (verilog);
     \draw[->,thick] (htl.west) to [out=180,in=150] (4,-2.2) to [out=330,in=270] (htl.south);
   \end{tikzpicture}%}
-  \caption{\vericert{} as a Verilog back end to \compcert{}. \JW{Did we ought to add CompCert's other back ends to the diagram? X86 etc? Otherwise it might look like we have a very out-of-date view of CompCert.}}%
+  \caption{\vericert{} as a Verilog back end to \compcert{}.
+%\JW{Did we ought to add CompCert's other back ends to the diagram? X86 etc? Otherwise it might look like we have a very out-of-date view of CompCert.}}%
   \label{fig:rtlbranch}
 \end{figure}