Fix formatting some more

1 files changed, 16 insertions, 14 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 6ab06c4..a4c7de9 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -28,12 +28,12 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
 
 \begin{figure}
   \centering
-  \resizebox{0.47\textwidth}{!}{
+  \resizebox{0.85\textwidth}{!}{
   \begin{tikzpicture}
     [language/.style={fill=white,rounded corners=3pt,minimum height=7mm},
     continuation/.style={}]
-    \fill[compcert,rounded corners=3pt] (-1,-1) rectangle (9,1.5);
-    \fill[formalhls,rounded corners=3pt] (-1,-1.5) rectangle (9,-2.5);
+    \fill[compcert,rounded corners=3pt] (-1,-0.5) rectangle (9,1.5);
+    \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9,-2);
     \node[language] at (-0.3,0) (clight) {Clight};
     \node[continuation] at (1,0) (conta) {$\cdots$};
     \node[language] at (2.7,0) (cminor) {CminorSel};
@@ -41,18 +41,20 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
     \node[language] at (6.2,0) (ltl) {LTL};
     \node[language] at (8.4,0) (ppc) {PPC};
     \node[continuation] at (7.3,0) (contb) {$\cdots$};
-    \node[language] at (4.7,-2) (dfgstmd) {HTL};
-    \node[language] at (6.7,-2) (verilog) {Verilog};
+    \node[language] at (4.7,-1.5) (htl) {HTL};
+    \node[language] at (6.7,-1.5) (verilog) {Verilog};
     \node at (0,1) {\bf\compcert{}};
-    \node at (0,-2) {\bf\vericert{}};
-    \draw[->] (clight) -- (conta);
-    \draw[->] (conta) -- (cminor);
-    \draw[->] (cminor) -- (rtl);
-    \draw[->] (rtl) -- (ltl);
-    \draw[->] (ltl) -- (contb);
-    \draw[->] (contb) -- (ppc);
-    \draw[->] (rtl) -- (dfgstmd);
-    \draw[->] (dfgstmd) -- (verilog);
+    \node at (0,-1.5) {\bf\vericert{}};
+    \node[align=center] at (3.3,-2.4) {\footnotesize Memory\\[-0.5em]\footnotesize Inferrence};
+    \draw[->,thick] (clight) -- (conta);
+    \draw[->,thick] (conta) -- (cminor);
+    \draw[->,thick] (cminor) -- (rtl);
+    \draw[->,thick] (rtl) -- (ltl);
+    \draw[->,thick] (ltl) -- (contb);
+    \draw[->,thick] (contb) -- (ppc);
+    \draw[->,thick] (rtl) -- (htl);
+    \draw[->,thick] (htl) -- (verilog);
+    \draw[->,thick] (htl.west) to [out=180,in=150] (4,-2.2) to [out=330,in=270] (htl.south);
   \end{tikzpicture}}
   \caption{\vericert{} as a Verilog back end to \compcert{}}%
   \label{fig:rtlbranch}