Add city and description

1 files changed, 4 insertions, 0 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 72a53aa..6282664 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -69,6 +69,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
     \draw[->,thick] (htl) -- (verilog);
     \draw[->,thick] (htl.west) to [out=180,in=150] (4,-2.2) to [out=330,in=270] (htl.south);
   \end{tikzpicture}%}
+  \Description{The compilation flow of \compcert{}, showing where \vericert{} branches off.}
   \caption{\vericert{} as a Verilog back end to \compcert{}.}%
   \label{fig:rtlbranch}
 \end{figure}
@@ -135,6 +136,7 @@ endmodule
       to [out=60,in=130] ($(s2.east) + (0.3,0.7)$) to [out=310,in=10] (s2);
     \end{tikzpicture}
   \end{subfigure}
+  \Description{Verilog code of a state machine, and its equivalent state machine diagram.}
   \caption{A simple state machine implemented in Verilog, with its diagrammatic representation on the right. The x's stand for don't cares and each transition is labelled with the values of the inputs \texttt{rst} and \texttt{y} that trigger the transition.  The output that will be produced is shown in each state.}%
   \label{fig:tutorial:state_machine}
 \end{figure}
@@ -358,6 +360,7 @@ Compared to plain Verilog, HTL is simpler to manipulate and analyse, thereby mak
   \node[scale=0.4] at (3.5,3.6) {\texttt{reg\_4}};
   \node[scale=0.4] at (3.5,3.4) {\texttt{reg\_5}};
 \end{tikzpicture}}
+  \Description{Diagram displaying the data-path and its internal modules, as well as the control logic and its state machine.}
   \caption{The FSMD for the example shown in Fig.~\ref{fig:accumulator_c_rtl}, split into a data-path and control logic for the next state calculation.  The Update block takes the current state, current values of all registers and at most one value stored in the RAM, and calculates a new value that can either be stored back in the  or in a register.}\label{fig:accumulator_diagram}
 \end{figure*}
 
@@ -460,6 +463,7 @@ Secondly, the logic in the enable signal of the RAM (\texttt{en != u\_en}) is al
     \end{tikztimingtable}
     \caption{Timing diagram for stores. At time 1, the \texttt{u\_en} signal is toggled to enable the RAM, and the address \texttt{addr} and the data to store \texttt{d\_in} are set. On the negative edge at time 2, the data is stored into the RAM.}\label{fig:ram_store}
   \end{subfigure}
+  \Description{Timing diagrams of loads and stores, showing which signals are modified at which time step.}
   \caption{Timing diagrams showing the execution of loads and stores over multiple clock cycles.}\label{fig:ram_load_store}
 \end{figure}