Make figure into one

1 files changed, 7 insertions, 15 deletions

diff --git a/algorithm.tex b/algorithm.tex
index 80131dc..0749e88 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -67,9 +67,9 @@ We select CompCert's three-address code (3AC)\footnote{This is known as register
 
 3AC is also attractive because it is the closest intermediate language to LLVM IR, which is used by several existing HLS compilers. It has an unlimited number of pseudo-registers, and is represented as a control flow graph (CFG) where each instruction is a node with links to the instructions that can follow it. One difference between LLVM IR and 3AC is that 3AC includes operations that are specific to the chosen target architecture; we chose x86\_32 because each instruction maps well to hardware.
 
-\begin{figure*}
+\begin{figure}
   \centering
-  \begin{subfigure}[b]{0.24\linewidth}
+  \begin{subfigure}[b]{0.49\linewidth}
 \begin{minted}{c}
 int main() {
   int x[3] = {1, 2, 3};
@@ -83,7 +83,7 @@ int main() {
 \end{minted}
     \caption{Input C code.}\label{fig:accumulator_c}
   \end{subfigure}\hspace*{-4mm}
-  \begin{subfigure}[b]{0.24\linewidth}
+  \begin{subfigure}[b]{0.49\linewidth}
 \begin{minted}[fontsize=\footnotesize]{c}
 main() {
  15:  x8 = 1
@@ -105,7 +105,8 @@ main() {
 \end{minted}
     \caption{3AC produced by \compcert{}.}\label{fig:accumulator_rtl}
   \end{subfigure}\hfill%
-\begin{subfigure}[b]{0.45\linewidth}
+\begin{subfigure}[b]{1\linewidth}
+\vspace{1em}
 \begin{minted}[fontsize=\tiny]{verilog}
 module main(reset, clk, finish, return_val);
   reg [31:0] stack [2:0];
@@ -171,10 +172,10 @@ module main(reset, clk, finish, return_val);
       endcase
 endmodule
 \end{minted}
-\caption{Verilog produce by \vericert{}.  The intermediate language HTL is an abstraction that uses maps from states to the Verilog statements instead of case statements.}\label{fig:accumulator_rtl}
+\caption{Verilog output for our running example, as generated by \vericert{}. The left column contains the datapath and the right column contains the control logic.}\label{fig:accumulator_v}
 \end{subfigure}
   \caption{Using \compcert{} to translate a simple program from C to three address code (3AC).}\label{fig:accumulator_c_rtl}
-\end{figure*}
+\end{figure}
 
 \subsection{Translating C to Verilog, by example}
 
@@ -298,15 +299,6 @@ For example, in state 15 in figure~\ref{fig:accumulator_rtl}, the register \text
 \paragraph{Key challenge: signedness} Note that the comparison in state 3 is signed. This is because C and Verilog handle signedness quite differently. By default, all operators and registers in Verilog (and HTL) are unsigned, so to force an operation to handle the bits as signed, both operators have to be forced to be signed.  In addition to that, Verilog resizes expressions to the largest needed size by default, which can affect the result of the computation.  This feature is also not supported by the Verilog semantics we adopted, and there would therefore be a mismatch between the Verilog semantics and the actual behaviour of Verilog according to the standard.  To bypass this issue, braces are used to stop the Verilog simulator or synthesis tool from resizing anything inside the braces.  Instead, explicit resizing is used in the semantics and operations can only be performed on two registers that
 have the same size.
 
-\begin{figure}
-  \centering
-  %\begin{subfigure}[b]{0.49\linewidth}
-
-    %\caption{Verilog always block describing the control logic of the module.}\label{fig:accumulator_v_2}
-  %\end{subfigure}
-  \caption{Verilog output for our running example, as generated by \vericert{}. The left column contains the datapath and the right column contains the control logic.}\label{fig:accumulator_v}
-\end{figure}
-
 \subsection{Translating HTL to Verilog}
 
 Finally, we have to translate the HTL code into proper Verilog. % and prove that it behaves the same as the 3AC according to the Verilog semantics.