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authorJohn Wickerson <j.wickerson@imperial.ac.uk>2021-08-31 11:31:45 +0000
committernode <node@git-bridge-prod-0>2021-08-31 15:38:19 +0000
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parent02cad5f3082fb3661a121be62c09b8356e36a584 (diff)
downloadoopsla21_fvhls-945414d6bacce6205136358766a44f50af6dfd65.tar.gz
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Update on Overleaf.
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diff --git a/algorithm.tex b/algorithm.tex
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@@ -133,7 +133,7 @@ endmodule
to [out=60,in=130] ($(s2.east) + (0.3,0.7)$) to [out=310,in=10] (s2);
\end{tikzpicture}
\end{subfigure}
- \caption{A simple state machine implemented in Verilog, with its diagrammatic representation on the right, where the x's stand for don't cares and each transition is labelled with the values for the \texttt{rst}, \texttt{y} and output \texttt{z}.}%
+ \caption{A simple state machine implemented in Verilog, with its diagrammatic representation on the right. The x's stand for don't cares and each transition is labelled with the values of the inputs \texttt{rst} and \texttt{y} and output \texttt{z}.}%
\label{fig:tutorial:state_machine}
\end{figure}