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author | John Wickerson <j.wickerson@imperial.ac.uk> | 2021-04-16 09:26:25 +0000 |
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committer | overleaf <overleaf@localhost> | 2021-04-16 09:26:30 +0000 |
commit | acabfc43a6a028f4712be741759c2f188c7370eb (patch) | |
tree | fea9b420f605ba2cbe587d651eafbf42e229d4c0 /algorithm.tex | |
parent | 2356ba391f76e0af75a6bb2570826b3ea00413de (diff) | |
download | oopsla21_fvhls-acabfc43a6a028f4712be741759c2f188c7370eb.tar.gz oopsla21_fvhls-acabfc43a6a028f4712be741759c2f188c7370eb.zip |
Update on Overleaf.
Diffstat (limited to 'algorithm.tex')
-rw-r--r-- | algorithm.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/algorithm.tex b/algorithm.tex index 1302d64..8e7f5b4 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -150,7 +150,7 @@ module main(reset, clk, finish, return_val); endcase endmodule \end{minted} -\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v} +\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the abso} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v} \end{subfigure} \caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl} \end{figure} |